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authorMatt Ettus <matt@ettus.com>2009-09-24 22:34:06 -0700
committerMatt Ettus <matt@ettus.com>2009-09-24 22:34:06 -0700
commit1b613dc7c995029b88391ffff768672d30149a1e (patch)
treee1a479a267d091e50f5e127a9458b846abdd6e0b /sdr_lib/hb_dec.v
parent622efe894fd4ec2fced85355029b879e5c1fb32f (diff)
parent618ebd292a5b0acf221ef2d4ccf1a19596bc6c86 (diff)
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Merge commit 'origin' into new_eth
Conflicts: .gitignore
Diffstat (limited to 'sdr_lib/hb_dec.v')
-rw-r--r--sdr_lib/hb_dec.v5
1 files changed, 3 insertions, 2 deletions
diff --git a/sdr_lib/hb_dec.v b/sdr_lib/hb_dec.v
index b256eb57f..8fb5ba222 100644
--- a/sdr_lib/hb_dec.v
+++ b/sdr_lib/hb_dec.v
@@ -9,6 +9,7 @@ module hb_dec
(input clk,
input rst,
input bypass,
+ input run,
input [8:0] cpi, // Clocks per input -- equal to the decimation ratio ahead of this block
input stb_in,
input [IWIDTH-1:0] data_in,
@@ -25,7 +26,7 @@ module hb_dec
assign do_mult = 1;
always @(posedge clk)
- if(rst)
+ if(rst | ~run)
odd <= 0;
else if(stb_in)
odd <= ~odd;
@@ -34,7 +35,7 @@ module hb_dec
assign write_even = stb_in & ~odd;
always @(posedge clk)
- if(rst)
+ if(rst | ~run)
phase <= 0;
else if(stb_in & odd)
phase <= 1;