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author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2006-08-03 04:51:51 +0000 |
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committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2006-08-03 04:51:51 +0000 |
commit | 4f523681b7e786694969bcb7bfddb68b976c8ab7 (patch) | |
tree | 8abf3004259c399ba18b7eea297c149bf2d980ce /sdr_lib/gen_sync.v | |
download | uhd-4f523681b7e786694969bcb7bfddb68b976c8ab7.tar.gz uhd-4f523681b7e786694969bcb7bfddb68b976c8ab7.tar.bz2 uhd-4f523681b7e786694969bcb7bfddb68b976c8ab7.zip |
Houston, we have a trunk.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3122 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'sdr_lib/gen_sync.v')
-rw-r--r-- | sdr_lib/gen_sync.v | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/sdr_lib/gen_sync.v b/sdr_lib/gen_sync.v new file mode 100644 index 000000000..d72b39d56 --- /dev/null +++ b/sdr_lib/gen_sync.v @@ -0,0 +1,43 @@ +// -*- verilog -*- +// +// USRP - Universal Software Radio Peripheral +// +// Copyright (C) 2003 Matt Ettus +// +// This program is free software; you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation; either version 2 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program; if not, write to the Free Software +// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA +// + +module gen_sync + ( input clock, + input reset, + input enable, + input [7:0] rate, + output wire sync ); + +// parameter width = 8; + + reg [7:0] counter; + assign sync = |(((rate+1)>>1)& counter); + + always @(posedge clock) + if(reset || ~enable) + counter <= #1 0; + else if(counter == rate) + counter <= #1 0; + else + counter <= #1 counter + 8'd1; + +endmodule // gen_sync + |