Adds capability to independently delay the Auto T/R switching signal by a configurable number of clock ticks, to allow users to precisely align their T/R output with the pipeline delays in the transmitter.

There are two new registers:

FR_ATR_TX_DELAY (7'd2)
FR_ATR_RX_DELAY (7'd3)

...and the corresponding db_base.py methods to set them:

db_base.set_atr_tx_delay(clock_ticks)
db_base.set_atr_rx_delay(clock_ticks)

These methods are inherited by all the daughterboard objects so you can
call them from your scripts as:

subdev.set_atr_tx_delay(...)

...where 'subdev' represents the daughtercard object you're working with.

The FPGA synthesis for the 2 RXHB, 2 TX case expands from 95% to 96%,
with no additional synthesis messages or impact on timing.



git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5022 221aa14e-8319-0410-a670-987f0aec2ac5

1 files changed, 83 insertions, 0 deletions

diff --git a/sdr_lib/atr_delay.v b/sdr_lib/atr_delay.v
new file mode 100644
index 000000000..a832421a1
--- /dev/null
+++ b/sdr_lib/atr_delay.v
@@ -0,0 +1,83 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2007 Corgan Enterprises LLC
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module atr_delay(clk_i,rst_i,ena_i,tx_empty_i,tx_delay_i,rx_delay_i,atr_tx_o);
+   input        clk_i;
+   input        rst_i;
+   input        ena_i;
+   input        tx_empty_i;
+   input [31:0] tx_delay_i;
+   input [31:0] rx_delay_i;
+   output       atr_tx_o;
+
+   reg [3:0] 	state;
+   reg [31:0] 	count;
+
+   `define ST_RX_DELAY 4'b0001
+   `define ST_RX       4'b0010
+   `define ST_TX_DELAY 4'b0100
+   `define ST_TX       4'b1000
+
+   always @(posedge clk_i)
+     if (rst_i | ~ena_i)
+       begin
+	  state <= `ST_RX;
+	  count <= 0;
+       end
+     else
+       case (state)
+	 `ST_RX:
+	   if (!tx_empty_i)
+	     begin
+		state <= `ST_TX_DELAY;
+		count <= tx_delay_i;
+	     end
+
+	 `ST_TX_DELAY:
+	   if (count == 0)
+	     state <= `ST_TX;
+	   else
+	     count <= count - 1;
+
+	 `ST_TX:
+	   if (tx_empty_i)
+	     begin
+		state <= `ST_RX_DELAY;
+		count <= rx_delay_i;
+	     end
+
+	 `ST_RX_DELAY:
+	   if (count == 0)
+	     state <= `ST_RX;
+	   else
+	     count <= count - 1;
+	 
+	 default:		// Error
+	   begin
+	      state <= `ST_RX;
+	      count <= 0;
+	   end
+       endcase
+   
+   assign atr_tx_o = (state == `ST_TX) | (state == `ST_RX_DELAY);
+   
+endmodule // atr_delay
+