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authorjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>2008-09-08 01:00:12 +0000
committerjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>2008-09-08 01:00:12 +0000
commit61f2f0214c5999ea42a368a4fc99f03d8eb28d1e (patch)
treee7e24a9adc05ff1422fe3ada9926a51634741b47 /sdr_lib/HB.sav
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Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'sdr_lib/HB.sav')
-rw-r--r--sdr_lib/HB.sav56
1 files changed, 56 insertions, 0 deletions
diff --git a/sdr_lib/HB.sav b/sdr_lib/HB.sav
new file mode 100644
index 000000000..c5087e8a6
--- /dev/null
+++ b/sdr_lib/HB.sav
@@ -0,0 +1,56 @@
+[size] 1400 967
+[pos] -1 -1
+*-46.395245 2565000000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] hb_dec_tb.
+@420
+hb_dec_tb.data_in[17:0]
+@28
+hb_dec_tb.strobe_in
+hb_dec_tb.strobe_out
+hb_dec_tb.uut.write_even
+@22
+hb_dec_tb.uut.addr_even[3:0]
+@420
+hb_dec_tb.uut.data_even[17:0]
+hb_dec_tb.uut.data_odd_a[17:0]
+hb_dec_tb.uut.data_odd_b[17:0]
+hb_dec_tb.uut.data_odd_c[17:0]
+hb_dec_tb.uut.data_odd_d[17:0]
+@28
+hb_dec_tb.uut.write_odd
+@420
+hb_dec_tb.uut.prod1[35:0]
+hb_dec_tb.uut.prod2[35:0]
+@24
+hb_dec_tb.uut.phase[2:0]
+@28
+hb_dec_tb.uut.stb_in
+hb_dec_tb.uut.stb_out
+@420
+hb_dec_tb.uut.sum2[17:0]
+hb_dec_tb.uut.stb_out_pre[15:0]
+@28
+hb_dec_tb.uut.do_acc
+hb_dec_tb.uut.clear
+@420
+hb_dec_tb.uut.sum1[17:0]
+hb_dec_tb.uut.coeff1[17:0]
+hb_dec_tb.uut.prod1[35:0]
+hb_dec_tb.uut.prod2[35:0]
+hb_dec_tb.uut.final_sum[17:0]
+hb_dec_tb.uut.coeff2[17:0]
+hb_dec_tb.uut.sum_of_prod[21:0]
+hb_dec_tb.data_out[17:0]
+@28
+hb_dec_tb.uut.do_acc
+hb_dec_tb.uut.clear
+@24
+hb_dec_tb.uut.addr_odd_a[3:0]
+hb_dec_tb.uut.addr_odd_b[3:0]
+hb_dec_tb.uut.addr_odd_c[3:0]
+hb_dec_tb.uut.addr_odd_d[3:0]
+@28
+hb_dec_tb.uut.write_odd
+hb_dec_tb.uut.write_even
+@22
+hb_dec_tb.uut.data_even[17:0]