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| author | Daniel Jepson <daniel.jepson@ni.com> | 2018-04-06 14:50:23 -0500 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2018-04-10 09:58:34 -0700 |
| commit | d107f0e7758fdea7a0b76a02c83cb33f760b66b0 (patch) | |
| tree | 709b5f3a86a2736dddf82161fdacc58e4e186e8e /mpm | |
| parent | e2f91203314efdc19e9027d302b37643c0503ca3 (diff) | |
| download | uhd-d107f0e7758fdea7a0b76a02c83cb33f760b66b0.tar.gz uhd-d107f0e7758fdea7a0b76a02c83cb33f760b66b0.tar.bz2 uhd-d107f0e7758fdea7a0b76a02c83cb33f760b66b0.zip | |
jesd: add rx and tx SYSREF delay control in MPM
Diffstat (limited to 'mpm')
| -rw-r--r-- | mpm/python/usrp_mpm/cores/nijesdcore.py | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/mpm/python/usrp_mpm/cores/nijesdcore.py b/mpm/python/usrp_mpm/cores/nijesdcore.py index 13fd25dbf..d6f465c53 100644 --- a/mpm/python/usrp_mpm/cores/nijesdcore.py +++ b/mpm/python/usrp_mpm/cores/nijesdcore.py @@ -53,6 +53,8 @@ class NIMgJESDCore(object): self.bypass_descrambler = False self.bypass_scrambler = True self.lmfc_divider = 20 # Number of FPGA clock cycles per LMFC period. + self.rx_sysref_delay = 8 # Cycles of delay added to RX SYSREF + self.tx_sysref_delay = 11 # Cycles of delay added to TX SYSREF self.tx_driver_swing = 0b1111 # See UG476, TXDIFFCTRL self.tx_precursor = 0b00000 # See UG476, TXPRECURSOR self.tx_postcursor = 0b00000 # See UG476, TXPOSTCURSOR @@ -209,7 +211,10 @@ class NIMgJESDCore(object): disable_bit = 0b1 if enable: disable_bit = 0b0 - reg_val = ((self.lmfc_divider-1) << 23) | (disable_bit << 6) + reg_val = ((self.lmfc_divider-1) << 23) | \ + ((self.rx_sysref_delay) << 16) | \ + ((self.tx_sysref_delay) << 8) | \ + (disable_bit << 6) self.log.trace("Setting SYSREF Capture reg: 0x{:08X}".format(reg_val)) self.regs.poke32(self.SYSREF_CAPTURE_CONTROL, reg_val) |