rh: change uio access to utilize with-as

2 files changed, 85 insertions, 79 deletions

diff --git a/mpm/python/usrp_mpm/dboard_manager/rh_init.py b/mpm/python/usrp_mpm/dboard_manager/rh_init.py
index 20a06d788..58e31e612 100644
--- a/mpm/python/usrp_mpm/dboard_manager/rh_init.py
+++ b/mpm/python/usrp_mpm/dboard_manager/rh_init.py
@@ -9,7 +9,7 @@ Helper class to initialize a Rhodium daughterboard
 
 from __future__ import print_function
 import time
-from usrp_mpm.sys_utils.uio import UIO
+from usrp_mpm.sys_utils.uio import open_uio
 from usrp_mpm.dboard_manager.lmk_rh import LMK04828Rh
 from usrp_mpm.dboard_manager.rh_periphs import DboardClockControl
 from usrp_mpm.cores import ClockSynchronizer
@@ -301,63 +301,71 @@ class RhodiumInitManager(object):
 
         # 1. Prerequisites
         # Open FPGA IP (Clock control and JESD core).
-        self.log.trace("Creating dboard clock control object")
-        db_clk_control = DboardClockControl(self.rh_class.radio_regs, self.log)
-        self.log.trace("Creating jesdcore object")
-        jesdcore = nijesdcore.NIJESDCore(self.rh_class.radio_regs, self.rh_class.slot_idx, **self.JESD_DEFAULT_ARGS)
-
         self.log.trace("Creating gain table object...")
         self.gain_table_loader = GainTableRh(
             self._spi_ifaces['cpld'],
             self._spi_ifaces['cpld_gain_loader'],
             self.log)
 
-        # 2. Initialize LMK and bringup clocks.
-        # Disable FPGA MMCM's outputs, and assert its reset.
-        db_clk_control.reset_mmcm()
-        # Always place the JESD204b cores in reset before modifying the clocks,
-        # otherwise high power or erroneous conditions could exist in the FPGA!
-        jesdcore.reset()
-        # Configure and bringup the LMK's clocks.
-        self.log.trace("Initializing LMK...")
-        self.rh_class.lmk = self._init_lmk(
-            self._spi_ifaces['lmk'],
-            self.rh_class.ref_clock_freq,
-            self.rh_class.sampling_clock_rate,
-            self._spi_ifaces['phase_dac'],
-            self.INIT_PHASE_DAC_WORD,
-            self.PHASE_DAC_SPI_ADDR
-        )
-        self.log.trace("LMK Initialized!")
-        # Deassert FPGA's MMCM reset, poll for lock, and enable outputs.
-        db_clk_control.enable_mmcm()
-
-        # 3. Synchronize DB Clocks.
-        # The clock synchronzation driver receives the master_clock_rate, which for
-        # Rhodium is half the sampling_clock_rate.
-        self._sync_db_clock(
-            self.rh_class.radio_regs,
-            self.rh_class.ref_clock_freq,
-            self.rh_class.sampling_clock_rate / 2,
-            args)
-
-        # 4. DAC Configuration.
-        self.dac.config()
-
-        # 5. ADC Configuration.
-        self.adc.config()
-
-        # 6-7. JESD204B Initialization.
-        self.init_jesd(jesdcore, self.rh_class.sampling_clock_rate)
-        # [Optional] Perform RX eyescan.
-        if perform_rx_eyescan:
-            self.log.info("Performing RX eye scan on ADC to FPGA link...")
-            self._rx_eyescan(jesdcore, args)
-        # [Optional] Perform TX PRBS test.
-        if perform_tx_prbs:
-            self.log.info("Performing TX PRBS-31 test on FPGA to DAC link...")
-            self._tx_prbs_test(jesdcore, args)
-        jesdcore = None # We are done using the jesdcore at this point.
+        with open_uio(
+            label="dboard-regs-{}".format(self.rh_class.slot_idx),
+            read_only=False
+        ) as radio_regs:
+            self.log.trace("Creating dboard clock control object")
+            db_clk_control = DboardClockControl(radio_regs, self.log)
+            self.log.trace("Creating jesdcore object")
+            jesdcore = nijesdcore.NIJESDCore(radio_regs,
+                                             self.rh_class.slot_idx,
+                                             **self.JESD_DEFAULT_ARGS)
+
+            # 2. Initialize LMK and bringup clocks.
+            # Disable FPGA MMCM's outputs, and assert its reset.
+            db_clk_control.reset_mmcm()
+            # Always place the JESD204b cores in reset before modifying the clocks,
+            # otherwise high power or erroneous conditions could exist in the FPGA!
+            jesdcore.reset()
+            # Configure and bringup the LMK's clocks.
+            self.log.trace("Initializing LMK...")
+            self.rh_class.lmk = self._init_lmk(
+                self._spi_ifaces['lmk'],
+                self.rh_class.ref_clock_freq,
+                self.rh_class.sampling_clock_rate,
+                self._spi_ifaces['phase_dac'],
+                self.INIT_PHASE_DAC_WORD,
+                self.PHASE_DAC_SPI_ADDR
+            )
+            self.log.trace("LMK Initialized!")
+            # Deassert FPGA's MMCM reset, poll for lock, and enable outputs.
+            db_clk_control.enable_mmcm()
+
+            # 3. Synchronize DB Clocks.
+            # The clock synchronzation driver receives the master_clock_rate, which for
+            # Rhodium is half the sampling_clock_rate.
+            self._sync_db_clock(
+                radio_regs,
+                self.rh_class.ref_clock_freq,
+                self.rh_class.sampling_clock_rate / 2,
+                args)
+
+            # 4. DAC Configuration.
+            self.dac.config()
+
+            # 5. ADC Configuration.
+            self.adc.config()
+
+            # 6-7. JESD204B Initialization.
+            self.init_jesd(jesdcore, self.rh_class.sampling_clock_rate)
+            # [Optional] Perform RX eyescan.
+            if perform_rx_eyescan:
+                self.log.info("Performing RX eye scan on ADC to FPGA link...")
+                self._rx_eyescan(jesdcore, args)
+            # [Optional] Perform TX PRBS test.
+            if perform_tx_prbs:
+                self.log.info("Performing TX PRBS-31 test on FPGA to DAC link...")
+                self._tx_prbs_test(jesdcore, args)
+            # Direct the garbage collector by removing our references
+            jesdcore = None
+            db_clk_control = None
 
         # 8. CPLD Gain Tables Initialization.
         self.gain_table_loader.init()
diff --git a/mpm/python/usrp_mpm/dboard_manager/rhodium.py b/mpm/python/usrp_mpm/dboard_manager/rhodium.py
index 81c67ffa3..5f1061184 100644
--- a/mpm/python/usrp_mpm/dboard_manager/rhodium.py
+++ b/mpm/python/usrp_mpm/dboard_manager/rhodium.py
@@ -21,7 +21,7 @@ from usrp_mpm.cores import nijesdcore
 from usrp_mpm.dboard_manager.adc_rh import AD9695Rh
 from usrp_mpm.dboard_manager.dac_rh import DAC37J82Rh
 from usrp_mpm.mpmlog import get_logger
-from usrp_mpm.sys_utils.uio import UIO
+from usrp_mpm.sys_utils.uio import open_uio
 from usrp_mpm.sys_utils.udev import get_eeprom_paths
 from usrp_mpm.bfrfs import BufferFS
 from usrp_mpm.sys_utils.dtoverlay import apply_overlay_safe, rm_overlay_safe
@@ -247,13 +247,6 @@ class Rhodium(DboardManagerBase):
                 key: self.spi_factories[key](self._spi_nodes[key])
                 for key in self._spi_nodes
             }
-        def _init_dboard_regs():
-            " Create a UIO object to talk to dboard regs "
-            self.log.trace("Getting UIO to talk to dboard regs...")
-            return UIO(
-                label="dboard-regs-{}".format(self.slot_idx),
-                read_only=False
-            )
         self._port_expander = TCA6408(_get_i2c_dev())
         self._daughterboard_gpio = FPGAtoDbGPIO(self.slot_idx)
         # TODO: applying the overlay without checking for the presence of the
@@ -263,15 +256,13 @@ class Rhodium(DboardManagerBase):
             apply_overlay_safe('n321')
             self._lo_dist = FPGAtoLoDist(_get_i2c_dev())
         except RuntimeError:
-            self._lo_dist = None                
+            self._lo_dist = None
         self.log.debug("Turning on Module and RF power supplies")
         self._power_on()
         self._spi_ifaces = _init_spi_devices()
         self.log.debug("Loaded SPI interfaces!")
         self.cpld = RhCPLD(self._spi_ifaces['cpld'], self.log)
         self.log.debug("Loaded CPLD interfaces!")
-        self.radio_regs = _init_dboard_regs()
-        self.radio_regs._open()
         # Create DAC interface (analog output is disabled).
         self.log.trace("Creating DAC control object...")
         self.dac = DAC37J82Rh(self.slot_idx, self._spi_ifaces['dac'], self.log)
@@ -479,7 +470,7 @@ class Rhodium(DboardManagerBase):
             direction, port_number, {True: "active", False: "terminated"}[enable]))
         self.log.trace("Net name: {0}, Pin value: {1}".format(pin_info[0], pin_val))
         self._lo_dist.set(pin_info[0], pin_val)
-        
+
     def is_lo_dist_present(self):
         return self._lo_dist is not None
 
@@ -501,15 +492,19 @@ class Rhodium(DboardManagerBase):
         # a clock is provided to the chip.
         self.dac.tx_enable(False)
         self.adc.power_down_channel(True)
-        # Clear the Sample Clock enables and place the MMCM in reset.
-        db_clk_control = DboardClockControl(self.radio_regs, self.log)
-        db_clk_control.reset_mmcm()
-        # Place the JESD204b core in reset, mainly to reset QPLL/CPLLs.
-        jesdcore = nijesdcore.NIJESDCore(self.radio_regs, self.slot_idx,
-                                         **RhodiumInitManager.JESD_DEFAULT_ARGS)
-        jesdcore.reset()
-        # The reference clock is handled elsewhere since it is a motherboard-
-        # level clock.
+        with open_uio(
+            label="dboard-regs-{}".format(slot_idx),
+            read_only=False
+        ) as radio_regs:
+            # Clear the Sample Clock enables and place the MMCM in reset.
+            db_clk_control = DboardClockControl(radio_regs, self.log)
+            db_clk_control.reset_mmcm()
+            # Place the JESD204b core in reset, mainly to reset QPLL/CPLLs.
+            jesdcore = nijesdcore.NIJESDCore(radio_regs, self.slot_idx,
+                                             **RhodiumInitManager.JESD_DEFAULT_ARGS)
+            jesdcore.reset()
+            # The reference clock is handled elsewhere since it is a motherboard-
+            # level clock.
 
     def _reinit(self, master_clock_rate):
         """
@@ -636,9 +631,12 @@ class Rhodium(DboardManagerBase):
         """
         Debug for reading out all JESD core registers via RPC shell
         """
-        radio_regs = UIO(label="dboard-regs-{}".format(self.slot_idx))
-        for i in range(0x2000, 0x2110, 0x10):
-            print(("0x%04X " % i), end=' ')
-            for j in range(0, 0x10, 0x4):
-                print(("%08X" % radio_regs.peek32(i + j)), end=' ')
-            print("")
+        with open_uio(
+            label="dboard-regs-{}".format(slot_idx),
+            read_only=False
+        ) as radio_regs:
+            for i in range(0x2000, 0x2110, 0x10):
+                print(("0x%04X " % i), end=' ')
+                for j in range(0, 0x10, 0x4):
+                    print(("%08X" % radio_regs.peek32(i + j)), end=' ')
+                print("")