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| author | Lane Kolbly <lane.kolbly@ni.com> | 2022-01-19 17:00:16 -0600 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2022-01-24 14:24:53 -0600 |
| commit | 3d045685aba50900f968c48c22759bd76c01bf0a (patch) | |
| tree | 25cdce73783e6e4ba70ae046cce6e935a68193ec /mpm | |
| parent | 4e2ca25c2778b38959f4a1063510243d0de6b765 (diff) | |
| download | uhd-3d045685aba50900f968c48c22759bd76c01bf0a.tar.gz uhd-3d045685aba50900f968c48c22759bd76c01bf0a.tar.bz2 uhd-3d045685aba50900f968c48c22759bd76c01bf0a.zip | |
mpm: x4xx: Align get/set_gpio_src mappings with HDMI pinouts
Diffstat (limited to 'mpm')
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/x4xx_dio_control.py | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/x4xx_dio_control.py b/mpm/python/usrp_mpm/periph_manager/x4xx_dio_control.py index 1dd1c8457..1ad6bfeb2 100644 --- a/mpm/python/usrp_mpm/periph_manager/x4xx_dio_control.py +++ b/mpm/python/usrp_mpm/periph_manager/x4xx_dio_control.py @@ -314,7 +314,7 @@ class DioControl: # -------------------------------------------------------------------------- # Helper methods # -------------------------------------------------------------------------- - def _map_to_register_bit(self, port, pin): + def _map_to_register_bit(self, port, pin, lift_portb = True): """ Maps a pin denoted in current mapping scheme to a corresponding bit in the register map. @@ -340,8 +340,9 @@ class DioControl: # map pin back to register bit bit = port_map.index(pin) - # lift register bit up by PORT_BIT_SIZE for port b - bit = bit if port == self.DIO_PORTS[0] else bit + self.PORT_BIT_SIZE + if lift_portb: + # lift register bit up by PORT_BIT_SIZE for port b + bit = bit if port == self.DIO_PORTS[0] else bit + self.PORT_BIT_SIZE return bit def _calc_register_value(self, register, port, pin, value): @@ -564,7 +565,7 @@ class DioControl: else: return self.X4XX_GPIO_SRC_USER_APP - return [get_gpio_src_i(i) for i in range(self.X4XX_GPIO_WIDTH)] + return [get_gpio_src_i(self._map_to_register_bit(bank, i, False)) for i in range(self.X4XX_GPIO_WIDTH)] def set_gpio_src(self, bank: str, src): """ @@ -605,6 +606,7 @@ class DioControl: self, bank, self.RADIO_DIO_CLASSIC_ATR_CONFIG_REGISTER) for pin_index, src_name in enumerate(src): + pin_index = self._map_to_register_bit(bank, pin_index, False) radio_srcs = [ item for sublist in self.X4XX_GPIO_SRC_RADIO for item in sublist] if src_name in radio_srcs: |