rh: general code cleanup

- Add default bandwidth range
- Add default mash order constant
- Delete MPM todos
- Cleanup whitespace in MPM python code
- Add docstring for is_lo_dist_present

3 files changed, 9 insertions, 8 deletions

diff --git a/mpm/python/usrp_mpm/dboard_manager/adc_rh.py b/mpm/python/usrp_mpm/dboard_manager/adc_rh.py
index 2befa011f..4ddc65350 100644
--- a/mpm/python/usrp_mpm/dboard_manager/adc_rh.py
+++ b/mpm/python/usrp_mpm/dboard_manager/adc_rh.py
@@ -99,7 +99,7 @@ class AD9695Rh(object):
         self.log.trace("Clock status readback: 0x{:X}".format(clock_status))
         if clock_status != 0x01:
             self.log.error("Input clock not detected")
-            raise RuntimeError("Input clock not detected for ADC")            
+            raise RuntimeError("Input clock not detected for ADC")
 
         self.log.trace("ADC Configuration.")
         self.pokes8((
diff --git a/mpm/python/usrp_mpm/dboard_manager/rh_periphs.py b/mpm/python/usrp_mpm/dboard_manager/rh_periphs.py
index 2d631e509..7df734f06 100644
--- a/mpm/python/usrp_mpm/dboard_manager/rh_periphs.py
+++ b/mpm/python/usrp_mpm/dboard_manager/rh_periphs.py
@@ -91,8 +91,8 @@ class FPGAtoLoDist(object):
             raise RuntimeError('LO distribution board revision did not match: Expected: {0} Actual: {1}'.format(self.EXPECTED_BOARD_REV, board_rev))
         self._gpios.set(self.pins.index('P6_8V_EN'), 1)
         if not poll_with_timeout(
-                lambda: bool(self._gpios.get(self.pins.index('P6_8V_PG'))), 
-                self.POWER_ON_TIMEOUT, 
+                lambda: bool(self._gpios.get(self.pins.index('P6_8V_PG'))),
+                self.POWER_ON_TIMEOUT,
                 self.POWER_ON_POLL_INTERVAL):
             self._gpios.set(self.pins.index('P6_8V_EN'), 0)
             raise RuntimeError('Power on failure for LO Distribution board')
@@ -201,8 +201,6 @@ class RhCPLD(object):
         """
         return (self.peek16(self.REG_DAC_ALARM) & 0x0001)
 
-    # TODO: add more control/status functionality to this class?
-
 
 class DboardClockControl(object):
     """
diff --git a/mpm/python/usrp_mpm/dboard_manager/rhodium.py b/mpm/python/usrp_mpm/dboard_manager/rhodium.py
index 743cf5668..9b9086c20 100644
--- a/mpm/python/usrp_mpm/dboard_manager/rhodium.py
+++ b/mpm/python/usrp_mpm/dboard_manager/rhodium.py
@@ -297,7 +297,6 @@ class Rhodium(BfrfsEEPROM, DboardManagerBase):
         self.log.trace("Selected EEPROM offset: %d", user_eeprom_offset)
         user_eeprom_data = open(eeprom_path, 'rb').read()[user_eeprom_offset:]
         self.log.trace("Total EEPROM size is: %d bytes", len(user_eeprom_data))
-        # FIXME verify EEPROM sectors
         return BufferFS(
             user_eeprom_data,
             max_size=eeprom_info.get('max_size'),
@@ -411,6 +410,10 @@ class Rhodium(BfrfsEEPROM, DboardManagerBase):
         self._lo_dist.set(pin_info[0], pin_val)
 
     def is_lo_dist_present(self):
+        """
+        Returns true if this daughterboard has a LO distribution board
+        attached and initialized, otherwise false.
+        """
         return self._lo_dist is not None
 
     ##########################################################################
@@ -500,14 +503,14 @@ class Rhodium(BfrfsEEPROM, DboardManagerBase):
             self.log.info("Re-initializing daughter board. This may take some time.")
             self._reinit(self.master_clock_rate)
             self.log.debug("Daughter board re-initialization done.")
-            
+
     def enable_tx_lowband_lo(self, enable):
         """
         Enables or disables the TX lowband LO output from the LMK on the
         daughterboard.
         """
         self.lmk.enable_tx_lb_lo(enable);
-        
+
     def enable_rx_lowband_lo(self, enable):
         """
         Enables or disables the RX lowband LO output from the LMK on the