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authorMartin Braun <martin.braun@ettus.com>2017-06-06 17:20:29 -0700
committerMartin Braun <martin.braun@ettus.com>2017-12-22 15:03:59 -0800
commit62e2c25107234ebefe9f2668e44e79d37cd5a2e0 (patch)
treed00950e0273b9551c93db75599fde5b03c709e9e /mpm
parent8e5f18dc8d582198c742b3bfa3953b861f761b85 (diff)
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eiscat: Minor logging update for clock sync
Diffstat (limited to 'mpm')
-rw-r--r--mpm/python/usrp_mpm/dboard_manager/eiscat.py4
1 files changed, 4 insertions, 0 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/eiscat.py b/mpm/python/usrp_mpm/dboard_manager/eiscat.py
index 0f58b6e7f..adbbd848f 100644
--- a/mpm/python/usrp_mpm/dboard_manager/eiscat.py
+++ b/mpm/python/usrp_mpm/dboard_manager/eiscat.py
@@ -491,6 +491,10 @@ class EISCAT(DboardManagerBase):
raise RuntimeError("Clock synchronizer measured an offset of {} ps!".format(
offset_error*1e12
))
+ else:
+ self.log.debug("Residual DAC offset error: {} ps.".format(
+ offset_error*1e12
+ ))
self.log.info("Clock Synchronization Complete!")
def _check_jesd_cores(db_clk_control, jesd_cores):
" Checks clocks are enabled; init the JESD core; throw on failure. "