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authorTrung N Tran <trung.tran@ettus.com>2017-07-27 16:05:33 -0700
committerMartin Braun <martin.braun@ettus.com>2017-12-22 15:04:00 -0800
commita745877cc9e3962dedb3f6b7c5db3382568fadee (patch)
tree8dee0cd3c894459ed32a58ec6b5ba7e1c069ee81 /mpm/python
parent1db37316ebe81786671739e6e297b2d47c9f4807 (diff)
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n310: gpio bist
Diffstat (limited to 'mpm/python')
-rwxr-xr-xmpm/python/n3xx_bist33
-rw-r--r--mpm/python/usrp_mpm/periph_manager/n310.py70
2 files changed, 97 insertions, 6 deletions
diff --git a/mpm/python/n3xx_bist b/mpm/python/n3xx_bist
index a05a08b3c..f529cb70b 100755
--- a/mpm/python/n3xx_bist
+++ b/mpm/python/n3xx_bist
@@ -469,14 +469,37 @@ class N310BIST(object):
- read_patterns: A list of patterns that were read back
"""
assert 'gpio' in self.tests_to_run
+ patterns = range(64)
if self.args.dry_run:
return True, {
- 'write_patterns': [0, 1, 2, 4],
- 'read_patterns': [0, 1, 2, 4],
+ 'write_patterns': patterns,
+ 'read_patterns': patterns,
}
- # FIXME implement
- sys.stderr.write("Test not implemented.\n")
- return True, {}
+ from usrp_mpm.periph_manager import n310
+ gpioTCA6424 = n310.TCA6424()
+ ddr1 = 0x03f
+ ddr2 = 0xfc0
+ half_GPIO_SIZE = 6
+ def _runGPIO(ddr, patterns):
+ gpioTCA6424.set("FPGA-GPIO-EN")
+ time.sleep(.5)
+ myGPIO = n310.FP_GPIO(ddr)
+ for pattern in patterns:
+ myGPIO.set_all(pattern)
+ time.sleep(0.1)
+ rb = myGPIO.get_all()
+ if pattern != rb:
+ return False, {'write_patterns': [pattern],
+ 'read_patterns': [rb]}
+ return True, {'write_patterns': list(patterns),
+ 'read_patterns': list(patterns)}
+ gpioTCA6424.reset("FPGA-GPIO-EN")
+ time.sleep(.5)
+ status, data = _runGPIO(ddr1, patterns)
+ if not status:
+ return status, data
+ status, data = _runGPIO(ddr2, patterns)
+ return status, data
def bist_temp(self):
"""
diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py
index f51762e52..26c6f2893 100644
--- a/mpm/python/usrp_mpm/periph_manager/n310.py
+++ b/mpm/python/usrp_mpm/periph_manager/n310.py
@@ -69,7 +69,7 @@ class TCA6424(object):
)
def __init__(self):
- self._gpios = SysFSGPIO('tca6424',0xFFE7FF, 0x86E7FF)
+ self._gpios = SysFSGPIO('tca6424', 0xFFE7FF, 0x86E7FF)
def set(self, name):
"""
@@ -92,6 +92,74 @@ class TCA6424(object):
assert name in self.pins
self._gpios.get(self.pins.index(name))
+class FP_GPIO(object):
+ """
+ Abstraction layer for the front panel GPIO
+ """
+ EMIO_BASE = 54
+ FP_GPIO_OFFSET = 32 # Bit offset within the ps_gpio_* pins
+
+ def __init__(self, ddr):
+ self._gpiosize = 12
+ self._offset = self.FP_GPIO_OFFSET + self.EMIO_BASE
+ self.usemask = 0xFFF
+ self.ddr = ddr
+ self._gpios = SysFSGPIO(
+ 'zynq_gpio',
+ self.usemask<<self._offset,
+ self.ddr<<self._offset
+ )
+
+ def set_all(self, value):
+ """
+ Assert all pin to the value.
+ This method will convert value into binary and take the first 6 bits
+ assign to 6pins.
+ """
+ bin_value = '{0:06b}'.format(value)
+ wr_value = bin_value[-(self._gpiosize):]
+ for i in range(self._gpiosize):
+ if (1<<i)&self.ddr:
+ self._gpios.set(self._offset+i, wr_value[i%6])
+
+ def set(self, index, value=None):
+ """
+ Assert a pin by index
+ """
+ assert index in range(self._gpiosize)
+ self._gpios.set(self._offset+index, value)
+
+ def reset_all(self):
+ """
+ Deassert all pins
+ """
+ for i in range(self._gpiosize):
+ self._gpios.reset(self._offset+i)
+
+ def reset(self, index):
+ """
+ Deassert a pin by index
+ """
+ assert index in range(self._gpiosize)
+ self._gpios.reset(self._offset+index)
+
+ def get_all(self):
+ """
+ Read back all pins
+ """
+ result = 0
+ for i in range(self._gpiosize):
+ if not (1<<i)&self.ddr:
+ value = self._gpios.get(self._offset+i)
+ result = (result<<1) | value
+ return result
+
+ def get(self, index):
+ """
+ Read back a pin by index
+ """
+ assert index in range(self._gpiosize)
+ return self._gpios.get(self._offset+index)
class n310(PeriphManagerBase):
"""