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authorMartin Braun <martin.braun@ettus.com>2017-08-09 13:22:27 -0700
committerMartin Braun <martin.braun@ettus.com>2017-12-22 15:04:00 -0800
commit8ee3da3ef9b812eda2ac3269927191e09916dc3c (patch)
tree710fcbc3bce67c3cb1f298e2f511c3c03bc770cf /mpm/python
parent8ecb09be8bafa06245f0e5af758d165d94aa140e (diff)
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mpm: n3xx: Don't set time and clock source without dboards
When there are no daughterboards present, clock and time source are meaningless. It's also possible that corresponding FPGA images are not loaded, in which case trying to set those could crash the system. Unless daughterboards are actually present, these settings won't get applied any more.
Diffstat (limited to 'mpm/python')
-rw-r--r--mpm/python/usrp_mpm/periph_manager/n310.py20
1 files changed, 14 insertions, 6 deletions
diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py
index c36de555c..a9c8076ca 100644
--- a/mpm/python/usrp_mpm/periph_manager/n310.py
+++ b/mpm/python/usrp_mpm/periph_manager/n310.py
@@ -229,12 +229,20 @@ class n310(PeriphManagerBase):
self._ext_clock_freq = float(
default_args.get('ext_clock_freq', N3XX_DEFAULT_EXT_CLOCK_FREQ)
)
- self.set_clock_source(
- default_args.get('clock_source', N3XX_DEFAULT_CLOCK_SOURCE)
- )
- self.set_time_source(
- default_args.get('time_source', N3XX_DEFAULT_TIME_SOURCE)
- )
+ if len(self.dboards) == 0:
+ self.log.warning(
+ "No dboards found, skipping setting clock and time source " \
+ "configuration."
+ )
+ self._clock_source = N3XX_DEFAULT_CLOCK_SOURCE
+ self._time_source = N3XX_DEFAULT_TIME_SOURCE
+ else:
+ self.set_clock_source(
+ default_args.get('clock_source', N3XX_DEFAULT_CLOCK_SOURCE)
+ )
+ self.set_time_source(
+ default_args.get('time_source', N3XX_DEFAULT_TIME_SOURCE)
+ )
def init(self, args):
"""