n310/eiscat: Removed 20 MHz as a valid ref clock frequency

3 files changed, 18 insertions, 9 deletions

diff --git a/mpm/python/usrp_mpm/dboard_manager/eiscat.py b/mpm/python/usrp_mpm/dboard_manager/eiscat.py
index b4ecd01dd..822923fbf 100644
--- a/mpm/python/usrp_mpm/dboard_manager/eiscat.py
+++ b/mpm/python/usrp_mpm/dboard_manager/eiscat.py
@@ -435,7 +435,7 @@ class EISCAT(DboardManagerBase):
         self.log = get_logger("EISCAT-{}".format(slot_idx))
         self.log.trace("Initializing EISCAT daughterboard, slot index {}".format(self.slot_idx))
         self.initialized = False
-        self.ref_clock_freq = 10e6
+        self.ref_clock_freq = 10e6 # This is the only supported clock rate
         # Define some attributes so that PyLint stays quiet:
         self.radio_regs = None
         self.jesd_cores = None
@@ -701,13 +701,13 @@ class EISCAT(DboardManagerBase):
         """
         Call this to notify the daughterboard about a change in reference clock
         """
-        if self.initialized and freq != self.ref_clock_freq:
-            self.log.warning(
-                "Attempting to update external reference clock frequency "
-                "after initialization! This will only take effect after "
-                "the daughterboard is re-initialized. Unsetting init flag now."
+        if freq != self.ref_clock_freq:
+            self.log.error(
+                "EISCAT daughterboard only supports a reference clock " \
+                "frequency of {} MHz".format(self.ref_clock_freq/1e6)
             )
-            self.initialized = False
-        self.ref_clock_freq = freq
+            raise RuntimeError("Invalid reference clock frequency: {}".format(
+                freq
+            ))
 
 
diff --git a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py
index 3affdc3e9..4bd9594d4 100644
--- a/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py
+++ b/mpm/python/usrp_mpm/dboard_manager/lmk_eiscat.py
@@ -28,7 +28,11 @@ class LMK04828EISCAT(LMK04828):
     def __init__(self, regs_iface, ref_clock_freq, slot=None):
         LMK04828.__init__(self, regs_iface, slot)
         self.log.trace("Using reference clock frequency {} MHz".format(ref_clock_freq/1e6))
-        assert ref_clock_freq in (10e6, 20e6)
+        if ref_clock_freq != 10e6:
+            error_msg = "Invalid reference clock frequency: {} MHz. " \
+                        "Must be 10 MHz.".format(ref_clock_freq)
+            self.log.error(error_msg)
+            raise RuntimeError(error_msg)
         self.ref_clock_freq = ref_clock_freq
         self.init()
         self.config()
diff --git a/mpm/python/usrp_mpm/periph_manager/n310.py b/mpm/python/usrp_mpm/periph_manager/n310.py
index 343bab707..24b2cc742 100644
--- a/mpm/python/usrp_mpm/periph_manager/n310.py
+++ b/mpm/python/usrp_mpm/periph_manager/n310.py
@@ -352,6 +352,9 @@ class n310(PeriphManagerBase):
             self._gpios.reset("CLK-MAINREF-SEL1")
         self._clock_source = clock_source
         ref_clk_freq = self.get_ref_clock_freq()
+        self.log.info("Reference clock frequency is: {} MHz".format(
+            ref_clk_freq/1e6
+        ))
         for slot, dboard in enumerate(self.dboards):
             if hasattr(dboard, 'update_ref_clock_freq'):
                 self.log.trace(
@@ -368,6 +371,8 @@ class n310(PeriphManagerBase):
         Will throw if it's not a valid value.
         """
         assert freq in (10e6, 20e6, 25e6)
+        self.log.debug("We've been told the external reference clock " \
+                       "frequency is {} MHz.".format(freq/1e6))
         self._ext_clock_freq = freq
 
     def get_ref_clock_freq(self):