mpm: dboard_manager: add more args to update_ref_clock_freq

Summary:
This change will allow correct args to pass from mboard to dboards,
that in turn can be useful for dboard manager.

Details:
In N310, the dboard manager needs the  time source to be updated before
calling update_ref_clock_source(), because it will trigger a reinit of
the dboard, for which the time_source is essential to determine correct
clock synchronizer settings.
The special case is the white rabbit time source needs a different
internal ref_clock_frequency for the clock synchronizer than the passed
in ref_clock_freq.

3 files changed, 10 insertions, 8 deletions

diff --git a/mpm/python/usrp_mpm/dboard_manager/base.py b/mpm/python/usrp_mpm/dboard_manager/base.py
index f7ba918f6..be37a6264 100644
--- a/mpm/python/usrp_mpm/dboard_manager/base.py
+++ b/mpm/python/usrp_mpm/dboard_manager/base.py
@@ -98,7 +98,7 @@ class DboardManagerBase(object):
         """
         return self.device_info.get("serial", "")
 
-    def update_ref_clock_freq(self, freq):
+    def update_ref_clock_freq(self, freq, **kwargs):
         """
         Call this function if the frequency of the reference clock changes.
         """
diff --git a/mpm/python/usrp_mpm/dboard_manager/magnesium.py b/mpm/python/usrp_mpm/dboard_manager/magnesium.py
index c67acdc55..275ee4ce2 100644
--- a/mpm/python/usrp_mpm/dboard_manager/magnesium.py
+++ b/mpm/python/usrp_mpm/dboard_manager/magnesium.py
@@ -463,7 +463,7 @@ class Magnesium(DboardManagerBase):
         " Return master clock rate (== sampling rate) "
         return self.master_clock_rate
 
-    def update_ref_clock_freq(self, freq):
+    def update_ref_clock_freq(self, freq, **kwargs):
         """
         Call this function if the frequency of the reference clock changes
         (the 10, 20, 25 MHz one).
@@ -480,6 +480,7 @@ class Magnesium(DboardManagerBase):
         self.log.trace("Changing ref clock frequency to %f MHz", freq/1e6)
         self.ref_clock_freq = freq
         if self._init_args is not None:
+            self._init_args = {**self._init_args, **kwargs}
             self._reinit(self.master_clock_rate)
 
 
diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx.py b/mpm/python/usrp_mpm/periph_manager/n3xx.py
index 2615284dd..ccdf29815 100644
--- a/mpm/python/usrp_mpm/periph_manager/n3xx.py
+++ b/mpm/python/usrp_mpm/periph_manager/n3xx.py
@@ -628,12 +628,13 @@ class n3xx(ZynqComponents, PeriphManagerBase):
                 raise RuntimeError("Failed to lock SFP timebase.")
         # Update the DB with the correct Ref Clock frequency and force a re-init.
         for slot, dboard in enumerate(self.dboards):
-            if hasattr(dboard, 'update_ref_clock_freq'):
-                self.log.trace(
-                    "Updating reference clock on dboard %d to %f MHz...",
-                    slot, ref_clk_freq/1e6
-                )
-                dboard.update_ref_clock_freq(ref_clk_freq)
+            self.log.trace(
+                "Updating reference clock on dboard %d to %f MHz...",
+                slot, ref_clk_freq/1e6
+            )
+            dboard.update_ref_clock_freq(ref_clk_freq,
+                time_source=time_source,
+                clock_source=clock_source)
 
     def set_ref_clock_freq(self, freq):
         """