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| author | Trung Tran <trung.tran@ettus.com> | 2018-10-17 15:59:30 -0700 |
|---|---|---|
| committer | Brent Stapleton <bstapleton@g.hmc.edu> | 2018-10-18 18:20:14 -0700 |
| commit | 0e30a5ca0872762a36be15f030a763c7f67dd003 (patch) | |
| tree | 5d8aaa5e2ee38943f61ac66ca2b9b8ea882289e1 /mpm/python | |
| parent | 327893e505c28e1daa20e1c38e2015ced5abe218 (diff) | |
| download | uhd-0e30a5ca0872762a36be15f030a763c7f67dd003.tar.gz uhd-0e30a5ca0872762a36be15f030a763c7f67dd003.tar.bz2 uhd-0e30a5ca0872762a36be15f030a763c7f67dd003.zip | |
mg: adding skip_rfic argument
This change to add skip_rfic as an device argument.
skip_rfic should be only used in ref_clock bist tests
to bring down the test time.
Diffstat (limited to 'mpm/python')
| -rw-r--r-- | mpm/python/usrp_mpm/dboard_manager/mg_init.py | 5 | ||||
| -rw-r--r-- | mpm/python/usrp_mpm/periph_manager/n3xx.py | 4 |
2 files changed, 6 insertions, 3 deletions
diff --git a/mpm/python/usrp_mpm/dboard_manager/mg_init.py b/mpm/python/usrp_mpm/dboard_manager/mg_init.py index 99caf6d46..62cc27a4f 100644 --- a/mpm/python/usrp_mpm/dboard_manager/mg_init.py +++ b/mpm/python/usrp_mpm/dboard_manager/mg_init.py @@ -551,8 +551,9 @@ class MagnesiumInitManager(object): self.log.debug( "Sample Clocks and Phase DAC Configured Successfully!") # Clocks and PPS are now fully active! - self.mykonos.set_master_clock_rate(master_clock_rate) - self.init_jesd(jesdcore, master_clock_rate, args) + if args.get('skip_rfic', None) == None: + self.mykonos.set_master_clock_rate(master_clock_rate) + self.init_jesd(jesdcore, master_clock_rate, args) jesdcore = None # Help with garbage collection # That's all that requires access to the dboard regs! return True diff --git a/mpm/python/usrp_mpm/periph_manager/n3xx.py b/mpm/python/usrp_mpm/periph_manager/n3xx.py index 245f739f5..48ad48a25 100644 --- a/mpm/python/usrp_mpm/periph_manager/n3xx.py +++ b/mpm/python/usrp_mpm/periph_manager/n3xx.py @@ -635,7 +635,9 @@ class n3xx(ZynqComponents, PeriphManagerBase): dboard.update_ref_clock_freq( ref_clk_freq, time_source=time_source, - clock_source=clock_source) + clock_source=clock_source, + skip_rfic= args.get('skip_rfic', None) + ) def set_ref_clock_freq(self, freq): """ |