n3xx: add support for 122.88 and 153.6 MHz sample clock rates

 - re-wrote portions of the LMK driver for flexible rates and configuration
 - tweaked TDC driver for compatibility and ease of debugging
 - updated comments and log statements throughout for uniformity

1 files changed, 42 insertions, 3 deletions

diff --git a/mpm/python/usrp_mpm/chips/lmk04828.py b/mpm/python/usrp_mpm/chips/lmk04828.py
index 121d855ca..3d979e65e 100644
--- a/mpm/python/usrp_mpm/chips/lmk04828.py
+++ b/mpm/python/usrp_mpm/chips/lmk04828.py
@@ -18,6 +18,7 @@
 LMK04828 parent driver class
 """
 
+import math
 from builtins import object
 from ..mpmlog import get_logger
 
@@ -48,7 +49,7 @@ class LMK04828(object):
         Read back the chip ID
         """
         chip_id = self.peek8(0x03)
-        self.log.trace("Read chip ID: {}".format(chip_id))
+        self.log.trace("Chip ID Readback: {}".format(chip_id))
         return chip_id
 
     def verify_chip_id(self):
@@ -57,7 +58,7 @@ class LMK04828(object):
         """
         chip_id = self.get_chip_id()
         if chip_id != self.LMK_CHIP_ID:
-            self.log.error("Wrong chip id 0x{:X}".format(chip_id))
+            self.log.error("Wrong Chip ID 0x{:X}".format(chip_id))
             return False
         return True
 
@@ -73,7 +74,7 @@ class LMK04828(object):
             """
             pll_lock_status = self.regs_iface.peek8(addr)
             if (pll_lock_status & 0x7) != 0x02:
-                self.log.warning("LMK {} reporting unlocked... Status: 0x{:x}".format(pll_id, pll_lock_status))
+                self.log.warning("{} reporting unlocked... Status: 0x{:x}".format(pll_id, pll_lock_status))
                 return False
             return True
         lock_status = \
@@ -81,3 +82,41 @@ class LMK04828(object):
                 check_pll_lock("PLL2", 0x183)
         return lock_status
 
+
+## Register bitfield definitions ##
+
+    def divide_to_cnth_cntl_reg(self, divide_val):
+        """
+        From the divider value, returns the CNTL and CNTH register value.
+        Split divider value in half. If odd, round up for the CNTL and down
+        for the CNTH based on the datasheet recommendation.
+        """
+        cntl = int(math.ceil( divide_val/2.0))
+        cnth = int(math.floor(divide_val/2.0))
+        reg_val = ((cnth & 0xF) << 4) | (cntl & 0xF)
+        self.log.trace("From divider value 0d{}, writing CNTH/L as 0x{:02X}."
+           .format(divide_val, reg_val))
+        return reg_val
+
+    def divide_to_reg(self, divide_val, in_drive = 0x1, out_drive = 0x1):
+        """
+        From the divider value, returns the register value combined with the other
+        register fields.
+        """
+        reg_val = (divide_val & 0x1F) | ((in_drive & 0x1) << 5) | ((out_drive & 0x1) << 6)
+        self.log.trace("From divider value 0d{}, writing divider register as 0x{:02X}."
+           .format(divide_val, reg_val))
+        return reg_val
+
+    def pll2_pre_to_reg(self, prescaler, osc_field = 0x01, xtal_en = 0x0, ref_2x_en = 0x0):
+        """
+        From the prescaler value, returns the register value combined with the other
+        register fields.
+        """
+        # valid prescaler values are 2-8, where 8 is represented as 0x00.
+        assert prescaler in range(2,8+1)
+        reg_val = ((prescaler & 0x07) << 5) | ((osc_field & 0x7) << 2) | ((xtal_en & 0x1) << 1) | ((ref_2x_en & 0x1) << 0)
+        self.log.trace("From prescaler value 0d{}, writing register as 0x{:02X}."
+           .format(prescaler, reg_val))
+        return reg_val
+