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author | Andrew Moch <Andrew.Moch@ni.com> | 2020-05-08 15:28:52 +0100 |
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committer | Wade Fife <wade.fife@ettus.com> | 2020-06-04 11:53:10 -0500 |
commit | 3f6ad749b06094b0e16b412a791ba3f2ac509600 (patch) | |
tree | 6468e31f0e994a40429cef9eb23ce34c0a8fc242 /mpm/python/CMakeLists.txt | |
parent | e62c93fe15feb807acb0772080d77e185f70494f (diff) | |
download | uhd-3f6ad749b06094b0e16b412a791ba3f2ac509600.tar.gz uhd-3f6ad749b06094b0e16b412a791ba3f2ac509600.tar.bz2 uhd-3f6ad749b06094b0e16b412a791ba3f2ac509600.zip |
fpga: lib: Fix writes in axil_regport_master
Previously, if a write occurred before the FIFO was ready then a
write could hang as the data channel would complete but leave the
address channel in a state where it would never complete. The fix is
to hold off acknowledging on the data channel until the FIFO is ready.
Diffstat (limited to 'mpm/python/CMakeLists.txt')
0 files changed, 0 insertions, 0 deletions