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authorAndrew Moch <Andrew.Moch@ni.com>2020-05-08 15:28:52 +0100
committerWade Fife <wade.fife@ettus.com>2020-06-04 11:53:10 -0500
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fpga: lib: Fix writes in axil_regport_master
Previously, if a write occurred before the FIFO was ready then a write could hang as the data channel would complete but leave the address channel in a state where it would never complete. The fix is to hold off acknowledging on the data channel until the FIFO is ready.
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