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author | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2006-08-03 04:51:51 +0000 |
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committer | jcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5> | 2006-08-03 04:51:51 +0000 |
commit | 4f523681b7e786694969bcb7bfddb68b976c8ab7 (patch) | |
tree | 8abf3004259c399ba18b7eea297c149bf2d980ce /models/fifo.v | |
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Houston, we have a trunk.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3122 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'models/fifo.v')
-rw-r--r-- | models/fifo.v | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/models/fifo.v b/models/fifo.v new file mode 100644 index 000000000..a04e7da6c --- /dev/null +++ b/models/fifo.v @@ -0,0 +1,81 @@ +// Model of FIFO in Altera + +module fifo( data, wrreq, rdreq, rdclk, wrclk, aclr, q, + rdfull, rdempty, rdusedw, wrfull, wrempty, wrusedw); + + parameter width = 16; + parameter depth = 1024; + parameter addr_bits = 10; + + //`define rd_req 0; // Set this to 0 for rd_ack, 1 for rd_req + + input [width-1:0] data; + input wrreq; + input rdreq; + input rdclk; + input wrclk; + input aclr; + output [width-1:0] q; + output rdfull; + output rdempty; + output reg [addr_bits-1:0] rdusedw; + output wrfull; + output wrempty; + output reg [addr_bits-1:0] wrusedw; + + reg [width-1:0] mem [0:depth-1]; + reg [addr_bits-1:0] rdptr; + reg [addr_bits-1:0] wrptr; + +`ifdef rd_req + reg [width-1:0] q; +`else + wire [width-1:0] q; +`endif + + integer i; + + always @( aclr) + begin + wrptr <= #1 0; + rdptr <= #1 0; + for(i=0;i<depth;i=i+1) + mem[i] <= #1 0; + end + + always @(posedge wrclk) + if(wrreq) + begin + wrptr <= #1 wrptr+1; + mem[wrptr] <= #1 data; + end + + always @(posedge rdclk) + if(rdreq) + begin + rdptr <= #1 rdptr+1; +`ifdef rd_req + q <= #1 mem[rdptr]; +`endif + end + +`ifdef rd_req +`else + assign q = mem[rdptr]; +`endif + + // Fix these + always @(posedge wrclk) + wrusedw <= #1 wrptr - rdptr; + + always @(posedge rdclk) + rdusedw <= #1 wrptr - rdptr; + + assign wrempty = (wrusedw == 0); + assign wrfull = (wrusedw == depth-1); + + assign rdempty = (rdusedw == 0); + assign rdfull = (rdusedw == depth-1); + +endmodule // fifo_1c_1k + |