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authorjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>2008-09-08 01:00:12 +0000
committerjcorgan <jcorgan@221aa14e-8319-0410-a670-987f0aec2ac5>2008-09-08 01:00:12 +0000
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Merged r9433:9527 from features/gr-usrp2 into trunk. Adds usrp2 and gr-usrp2 top-level components. Trunk passes distcheck with mb-gcc installed, but currently not without them. The key issue is that when mb-gcc is not installed, the build system skips over the usrp2/firmware directory, and the firmware include files don't get put into the dist tarball. But we can't do the usual DIST_SUBDIRS method as the firmware is a subpackage.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9528 221aa14e-8319-0410-a670-987f0aec2ac5
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+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/SRL16E.v,v 1.7 2005/03/14 22:32:58 yanx Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+// ____ ____
+// / /\/ /
+// /___/ \ / Vendor : Xilinx
+// \ \ \/ Version : 8.1i (I.13)
+// \ \ Description : Xilinx Functional Simulation Library Component
+// / / 16-Bit Shift Register Look-Up-Table with Clock Enable
+// /___/ /\ Filename : SRL16E.v
+// \ \ / \ Timestamp : Thu Mar 25 16:43:40 PST 2004
+// \___\/\___\
+//
+// Revision:
+// 03/23/04 - Initial version.
+// End Revision
+
+`timescale 1 ps / 1 ps
+
+
+module SRL16E (Q, A0, A1, A2, A3, CE, CLK, D);
+
+ parameter INIT = 16'h0000;
+
+ output Q;
+
+ input A0, A1, A2, A3, CE, CLK, D;
+
+ reg [15:0] data;
+
+
+ assign Q = data[{A3, A2, A1, A0}];
+
+ initial
+ begin
+ assign data = INIT;
+ while (CLK === 1'b1 || CLK===1'bX)
+ #10;
+ deassign data;
+ end
+
+ always @(posedge CLK)
+ begin
+ if (CE == 1'b1) begin
+ {data[15:0]} <= #100 {data[14:0], D};
+ end
+ end
+
+
+endmodule
+