Merged features/inband -r4812:5218 into trunk. This group of changes includes:

 * working stand-alone mblock code
 * work-in-progress on usrp inband signaling

usrp now depends on mblock, and guile is a dependency.



git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5221 221aa14e-8319-0410-a670-987f0aec2ac5

5 files changed, 490 insertions, 0 deletions

diff --git a/megacells/fifo_512.bsf b/megacells/fifo_512.bsf
new file mode 100755
index 000000000..a955b5655
--- /dev/null
+++ b/megacells/fifo_512.bsf
@@ -0,0 +1,116 @@
+/*

+WARNING: Do NOT edit the input and output ports in this file in a text

+editor if you plan to continue editing the block that represents it in

+the Block Editor! File corruption is VERY likely to occur.

+*/

+/*

+Copyright (C) 1991-2006 Altera Corporation

+Your use of Altera Corporation's design tools, logic functions 

+and other software and tools, and its AMPP partner logic 

+functions, and any output files any of the foregoing 

+(including device programming or simulation files), and any 

+associated documentation or information are expressly subject 

+to the terms and conditions of the Altera Program License 

+Subscription Agreement, Altera MegaCore Function License 

+Agreement, or other applicable license agreement, including, 

+without limitation, that your use is for the sole purpose of 

+programming logic devices manufactured by Altera and sold by 

+Altera or its authorized distributors.  Please refer to the 

+applicable agreement for further details.

+*/

+(header "symbol" (version "1.1"))

+(symbol

+	(rect 0 0 160 184)

+	(text "fifo_512" (rect 58 1 109 17)(font "Arial" (font_size 10)))

+	(text "inst" (rect 8 168 25 180)(font "Arial" ))

+	(port

+		(pt 0 32)

+		(input)

+		(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))

+		(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))

+		(line (pt 0 32)(pt 16 32)(line_width 3))

+	)

+	(port

+		(pt 0 56)

+		(input)

+		(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))

+		(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))

+		(line (pt 0 56)(pt 16 56)(line_width 1))

+	)

+	(port

+		(pt 0 72)

+		(input)

+		(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))

+		(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))

+		(line (pt 0 72)(pt 16 72)(line_width 1))

+	)

+	(port

+		(pt 0 104)

+		(input)

+		(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))

+		(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))

+		(line (pt 0 104)(pt 16 104)(line_width 1))

+	)

+	(port

+		(pt 0 120)

+		(input)

+		(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))

+		(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))

+		(line (pt 0 120)(pt 16 120)(line_width 1))

+	)

+	(port

+		(pt 0 160)

+		(input)

+		(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))

+		(text "aclr" (rect 20 154 37 167)(font "Arial" (font_size 8)))

+		(line (pt 0 160)(pt 16 160)(line_width 1))

+	)

+	(port

+		(pt 160 40)

+		(output)

+		(text "wrfull" (rect 0 0 33 14)(font "Arial" (font_size 8)))

+		(text "wrfull" (rect 113 34 138 47)(font "Arial" (font_size 8)))

+		(line (pt 160 40)(pt 144 40)(line_width 1))

+	)

+	(port

+		(pt 160 56)

+		(output)

+		(text "wrempty" (rect 0 0 50 14)(font "Arial" (font_size 8)))

+		(text "wrempty" (rect 98 50 137 63)(font "Arial" (font_size 8)))

+		(line (pt 160 56)(pt 144 56)(line_width 1))

+	)

+	(port

+		(pt 160 96)

+		(output)

+		(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))

+		(text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size 8)))

+		(line (pt 160 96)(pt 144 96)(line_width 3))

+	)

+	(port

+		(pt 160 120)

+		(output)

+		(text "rdfull" (rect 0 0 28 14)(font "Arial" (font_size 8)))

+		(text "rdfull" (rect 117 114 141 127)(font "Arial" (font_size 8)))

+		(line (pt 160 120)(pt 144 120)(line_width 1))

+	)

+	(port

+		(pt 160 136)

+		(output)

+		(text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))

+		(text "rdempty" (rect 102 130 140 143)(font "Arial" (font_size 8)))

+		(line (pt 160 136)(pt 144 136)(line_width 1))

+	)

+	(drawing

+		(text "32 bits x 128 words" (rect 63 156 144 168)(font "Arial" ))

+		(line (pt 16 16)(pt 144 16)(line_width 1))

+		(line (pt 144 16)(pt 144 168)(line_width 1))

+		(line (pt 144 168)(pt 16 168)(line_width 1))

+		(line (pt 16 168)(pt 16 16)(line_width 1))

+		(line (pt 16 84)(pt 144 84)(line_width 1))

+		(line (pt 16 148)(pt 144 148)(line_width 1))

+		(line (pt 16 66)(pt 22 72)(line_width 1))

+		(line (pt 22 72)(pt 16 78)(line_width 1))

+		(line (pt 16 114)(pt 22 120)(line_width 1))

+		(line (pt 22 120)(pt 16 126)(line_width 1))

+	)

+)

diff --git a/megacells/fifo_512.cmp b/megacells/fifo_512.cmp
new file mode 100755
index 000000000..86fc07846
--- /dev/null
+++ b/megacells/fifo_512.cmp
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2006 Altera Corporation

+--Your use of Altera Corporation's design tools, logic functions 

+--and other software and tools, and its AMPP partner logic 

+--functions, and any output files any of the foregoing 

+--(including device programming or simulation files), and any 

+--associated documentation or information are expressly subject 

+--to the terms and conditions of the Altera Program License 

+--Subscription Agreement, Altera MegaCore Function License 

+--Agreement, or other applicable license agreement, including, 

+--without limitation, that your use is for the sole purpose of 

+--programming logic devices manufactured by Altera and sold by 

+--Altera or its authorized distributors.  Please refer to the 

+--applicable agreement for further details.

+

+

+component fifo_512

+	PORT

+	(

+		aclr		: IN STD_LOGIC  := '0';

+		data		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);

+		rdclk		: IN STD_LOGIC ;

+		rdreq		: IN STD_LOGIC ;

+		wrclk		: IN STD_LOGIC ;

+		wrreq		: IN STD_LOGIC ;

+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

+		rdempty		: OUT STD_LOGIC ;

+		rdfull		: OUT STD_LOGIC ;

+		wrempty		: OUT STD_LOGIC ;

+		wrfull		: OUT STD_LOGIC 

+	);

+end component;

diff --git a/megacells/fifo_512.inc b/megacells/fifo_512.inc
new file mode 100755
index 000000000..9ae1e3af4
--- /dev/null
+++ b/megacells/fifo_512.inc
@@ -0,0 +1,32 @@
+--Copyright (C) 1991-2006 Altera Corporation

+--Your use of Altera Corporation's design tools, logic functions 

+--and other software and tools, and its AMPP partner logic 

+--functions, and any output files any of the foregoing 

+--(including device programming or simulation files), and any 

+--associated documentation or information are expressly subject 

+--to the terms and conditions of the Altera Program License 

+--Subscription Agreement, Altera MegaCore Function License 

+--Agreement, or other applicable license agreement, including, 

+--without limitation, that your use is for the sole purpose of 

+--programming logic devices manufactured by Altera and sold by 

+--Altera or its authorized distributors.  Please refer to the 

+--applicable agreement for further details.

+

+

+FUNCTION fifo_512 

+(

+	aclr,

+	data[31..0],

+	rdclk,

+	rdreq,

+	wrclk,

+	wrreq

+)

+

+RETURNS (

+	q[31..0],

+	rdempty,

+	rdfull,

+	wrempty,

+	wrfull

+);

diff --git a/megacells/fifo_512.v b/megacells/fifo_512.v
new file mode 100755
index 000000000..b034b4ddc
--- /dev/null
+++ b/megacells/fifo_512.v
@@ -0,0 +1,180 @@
+// megafunction wizard: %LPM_FIFO+%

+// GENERATION: STANDARD

+// VERSION: WM1.0

+// MODULE: dcfifo 

+

+// ============================================================

+// File Name: fifo_512.v

+// Megafunction Name(s):

+// 			dcfifo

+// ============================================================

+// ************************************************************

+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

+//

+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition

+// ************************************************************

+

+

+//Copyright (C) 1991-2006 Altera Corporation

+//Your use of Altera Corporation's design tools, logic functions 

+//and other software and tools, and its AMPP partner logic 

+//functions, and any output files any of the foregoing 

+//(including device programming or simulation files), and any 

+//associated documentation or information are expressly subject 

+//to the terms and conditions of the Altera Program License 

+//Subscription Agreement, Altera MegaCore Function License 

+//Agreement, or other applicable license agreement, including, 

+//without limitation, that your use is for the sole purpose of 

+//programming logic devices manufactured by Altera and sold by 

+//Altera or its authorized distributors.  Please refer to the 

+//applicable agreement for further details.

+

+

+// synopsys translate_off

+`timescale 1 ps / 1 ps

+// synopsys translate_on

+module fifo_512 (

+	aclr,

+	data,

+	rdclk,

+	rdreq,

+	wrclk,

+	wrreq,

+	q,

+	rdempty,

+	rdfull,

+	wrempty,

+	wrfull);

+

+	input	  aclr;

+	input	[31:0]  data;

+	input	  rdclk;

+	input	  rdreq;

+	input	  wrclk;

+	input	  wrreq;

+	output	[31:0]  q;

+	output	  rdempty;

+	output	  rdfull;

+	output	  wrempty;

+	output	  wrfull;

+

+	wire  sub_wire0;

+	wire  sub_wire1;

+	wire  sub_wire2;

+	wire  sub_wire3;

+	wire [31:0] sub_wire4;

+	wire  rdfull = sub_wire0;

+	wire  rdempty = sub_wire1;

+	wire  wrfull = sub_wire2;

+	wire  wrempty = sub_wire3;

+	wire [31:0] q = sub_wire4[31:0];

+

+	dcfifo	dcfifo_component (

+				.wrclk (wrclk),

+				.rdreq (rdreq),

+				.aclr (aclr),

+				.rdclk (rdclk),

+				.wrreq (wrreq),

+				.data (data),

+				.rdfull (sub_wire0),

+				.rdempty (sub_wire1),

+				.wrfull (sub_wire2),

+				.wrempty (sub_wire3),

+				.q (sub_wire4)

+				// synopsys translate_off

+				,

+				.rdusedw (),

+				.wrusedw ()

+				// synopsys translate_on

+				);

+	defparam

+		dcfifo_component.add_ram_output_register = "OFF",

+		dcfifo_component.clocks_are_synchronized = "FALSE",

+		dcfifo_component.intended_device_family = "Cyclone",

+		dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",

+		dcfifo_component.lpm_numwords = 128,

+		dcfifo_component.lpm_showahead = "OFF",

+		dcfifo_component.lpm_type = "dcfifo",

+		dcfifo_component.lpm_width = 32,

+		dcfifo_component.lpm_widthu = 7,

+		dcfifo_component.overflow_checking = "ON",

+		dcfifo_component.underflow_checking = "ON",

+		dcfifo_component.use_eab = "ON";

+

+

+endmodule

+

+// ============================================================

+// CNX file retrieval info

+// ============================================================

+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"

+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"

+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"

+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"

+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"

+// Retrieval info: PRIVATE: Clock NUMERIC "4"

+// Retrieval info: PRIVATE: Depth NUMERIC "128"

+// Retrieval info: PRIVATE: Empty NUMERIC "1"

+// Retrieval info: PRIVATE: Full NUMERIC "1"

+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"

+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"

+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"

+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"

+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"

+// Retrieval info: PRIVATE: Optimize NUMERIC "2"

+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"

+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"

+// Retrieval info: PRIVATE: UsedW NUMERIC "1"

+// Retrieval info: PRIVATE: Width NUMERIC "32"

+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"

+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"

+// Retrieval info: PRIVATE: rsFull NUMERIC "1"

+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"

+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"

+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"

+// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"

+// Retrieval info: PRIVATE: wsFull NUMERIC "1"

+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"

+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"

+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"

+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"

+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"

+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"

+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"

+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"

+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"

+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"

+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"

+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"

+// Retrieval info: CONSTANT: USE_EAB STRING "ON"

+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr

+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]

+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]

+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk

+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty

+// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull

+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq

+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk

+// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty

+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull

+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq

+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0

+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0

+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0

+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0

+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0

+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0

+// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0

+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0

+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0

+// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0

+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0

+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.v TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.inc TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.cmp TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.bsf TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_inst.v TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_bb.v TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_waveforms.html TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_wave*.jpg FALSE

diff --git a/megacells/fifo_512_bb.v b/megacells/fifo_512_bb.v
new file mode 100755
index 000000000..b11803159
--- /dev/null
+++ b/megacells/fifo_512_bb.v
@@ -0,0 +1,131 @@
+// megafunction wizard: %LPM_FIFO+%VBB%

+// GENERATION: STANDARD

+// VERSION: WM1.0

+// MODULE: dcfifo 

+

+// ============================================================

+// File Name: fifo_512.v

+// Megafunction Name(s):

+// 			dcfifo

+// ============================================================

+// ************************************************************

+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

+//

+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition

+// ************************************************************

+

+//Copyright (C) 1991-2006 Altera Corporation

+//Your use of Altera Corporation's design tools, logic functions 

+//and other software and tools, and its AMPP partner logic 

+//functions, and any output files any of the foregoing 

+//(including device programming or simulation files), and any 

+//associated documentation or information are expressly subject 

+//to the terms and conditions of the Altera Program License 

+//Subscription Agreement, Altera MegaCore Function License 

+//Agreement, or other applicable license agreement, including, 

+//without limitation, that your use is for the sole purpose of 

+//programming logic devices manufactured by Altera and sold by 

+//Altera or its authorized distributors.  Please refer to the 

+//applicable agreement for further details.

+

+module fifo_512 (

+	aclr,

+	data,

+	rdclk,

+	rdreq,

+	wrclk,

+	wrreq,

+	q,

+	rdempty,

+	rdfull,

+	wrempty,

+	wrfull);

+

+	input	  aclr;

+	input	[31:0]  data;

+	input	  rdclk;

+	input	  rdreq;

+	input	  wrclk;

+	input	  wrreq;

+	output	[31:0]  q;

+	output	  rdempty;

+	output	  rdfull;

+	output	  wrempty;

+	output	  wrfull;

+

+endmodule

+

+// ============================================================

+// CNX file retrieval info

+// ============================================================

+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"

+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"

+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"

+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"

+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"

+// Retrieval info: PRIVATE: Clock NUMERIC "4"

+// Retrieval info: PRIVATE: Depth NUMERIC "128"

+// Retrieval info: PRIVATE: Empty NUMERIC "1"

+// Retrieval info: PRIVATE: Full NUMERIC "1"

+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"

+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"

+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"

+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"

+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"

+// Retrieval info: PRIVATE: Optimize NUMERIC "2"

+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"

+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"

+// Retrieval info: PRIVATE: UsedW NUMERIC "1"

+// Retrieval info: PRIVATE: Width NUMERIC "32"

+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"

+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"

+// Retrieval info: PRIVATE: rsFull NUMERIC "1"

+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"

+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"

+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"

+// Retrieval info: PRIVATE: wsEmpty NUMERIC "1"

+// Retrieval info: PRIVATE: wsFull NUMERIC "1"

+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"

+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"

+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"

+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"

+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"

+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "128"

+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"

+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"

+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"

+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "7"

+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"

+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"

+// Retrieval info: CONSTANT: USE_EAB STRING "ON"

+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr

+// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]

+// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]

+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk

+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty

+// Retrieval info: USED_PORT: rdfull 0 0 0 0 OUTPUT NODEFVAL rdfull

+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq

+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk

+// Retrieval info: USED_PORT: wrempty 0 0 0 0 OUTPUT NODEFVAL wrempty

+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull

+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq

+// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0

+// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0

+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0

+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0

+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0

+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0

+// Retrieval info: CONNECT: rdfull 0 0 0 0 @rdfull 0 0 0 0

+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0

+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0

+// Retrieval info: CONNECT: wrempty 0 0 0 0 @wrempty 0 0 0 0

+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0

+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.v TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.inc TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.cmp TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512.bsf TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_inst.v TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_bb.v TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_waveforms.html TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_512_wave*.jpg FALSE