summaryrefslogtreecommitdiffstats
path: root/megacells/fifo_512.cmp
diff options
context:
space:
mode:
authoreb <eb@221aa14e-8319-0410-a670-987f0aec2ac5>2007-05-02 04:08:47 +0000
committereb <eb@221aa14e-8319-0410-a670-987f0aec2ac5>2007-05-02 04:08:47 +0000
commitb535098017d3df071b031bd15452a7bba53aab14 (patch)
tree24b141edd2f7d57562ae2e2ad05502b7852ad06f /megacells/fifo_512.cmp
parent5a17f48e7374466b10787ef2721166b1bb862cf1 (diff)
downloaduhd-b535098017d3df071b031bd15452a7bba53aab14.tar.gz
uhd-b535098017d3df071b031bd15452a7bba53aab14.tar.bz2
uhd-b535098017d3df071b031bd15452a7bba53aab14.zip
Merged features/inband -r4812:5218 into trunk. This group of changes includes:
* working stand-alone mblock code * work-in-progress on usrp inband signaling usrp now depends on mblock, and guile is a dependency. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@5221 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'megacells/fifo_512.cmp')
-rwxr-xr-xmegacells/fifo_512.cmp31
1 files changed, 31 insertions, 0 deletions
diff --git a/megacells/fifo_512.cmp b/megacells/fifo_512.cmp
new file mode 100755
index 000000000..86fc07846
--- /dev/null
+++ b/megacells/fifo_512.cmp
@@ -0,0 +1,31 @@
+--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+component fifo_512
+ PORT
+ (
+ aclr : IN STD_LOGIC := '0';
+ data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdclk : IN STD_LOGIC ;
+ rdreq : IN STD_LOGIC ;
+ wrclk : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ rdempty : OUT STD_LOGIC ;
+ rdfull : OUT STD_LOGIC ;
+ wrempty : OUT STD_LOGIC ;
+ wrfull : OUT STD_LOGIC
+ );
+end component;