Houston, we have a trunk.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@3122 221aa14e-8319-0410-a670-987f0aec2ac5

1 files changed, 3495 insertions, 0 deletions

diff --git a/megacells/fifo_4k.v b/megacells/fifo_4k.v
new file mode 100644
index 000000000..a5ab46677
--- /dev/null
+++ b/megacells/fifo_4k.v
@@ -0,0 +1,3495 @@
+// megafunction wizard: %FIFO%CBX%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: dcfifo 
+
+// ============================================================
+// File Name: fifo_4k.v
+// Megafunction Name(s):
+// 			dcfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.0 Build 168 06/22/2005 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2005 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic       
+//functions, and any output files any of the foregoing           
+//(including device programming or simulation files), and any    
+//associated documentation or information are expressly subject  
+//to the terms and conditions of the Altera Program License      
+//Subscription Agreement, Altera MegaCore Function License       
+//Agreement, or other applicable license agreement, including,   
+//without limitation, that your use is for the sole purpose of   
+//programming logic devices manufactured by Altera and sold by   
+//Altera or its authorized distributors.  Please refer to the    
+//applicable agreement for further details.
+
+
+//dcfifo ADD_RAM_OUTPUT_REGISTER="OFF" CLOCKS_ARE_SYNCHRONIZED="FALSE" DEVICE_FAMILY="Cyclone" LPM_NUMWORDS=4096 LPM_SHOWAHEAD="ON" LPM_WIDTH=16 LPM_WIDTHU=12 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" aclr data q rdclk rdempty rdreq rdusedw wrclk wrfull wrreq wrusedw
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+
+//a_gray2bin device_family="Cyclone" WIDTH=12 bin gray
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_mgl 2005:05:19:13:51:58:SJ  VERSION_END
+
+//synthesis_resources = 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_a_gray2bin_9m4
+	( 
+	bin,
+	gray) /* synthesis synthesis_clearbox=1 */;
+	output   [11:0]  bin;
+	input   [11:0]  gray;
+
+	wire  xor0;
+	wire  xor1;
+	wire  xor10;
+	wire  xor2;
+	wire  xor3;
+	wire  xor4;
+	wire  xor5;
+	wire  xor6;
+	wire  xor7;
+	wire  xor8;
+	wire  xor9;
+
+	assign
+		bin = {gray[11], xor10, xor9, xor8, xor7, xor6, xor5, xor4, xor3, xor2, xor1, xor0},
+		xor0 = (gray[0] ^ xor1),
+		xor1 = (gray[1] ^ xor2),
+		xor10 = (gray[11] ^ gray[10]),
+		xor2 = (gray[2] ^ xor3),
+		xor3 = (gray[3] ^ xor4),
+		xor4 = (gray[4] ^ xor5),
+		xor5 = (gray[5] ^ xor6),
+		xor6 = (gray[6] ^ xor7),
+		xor7 = (gray[7] ^ xor8),
+		xor8 = (gray[8] ^ xor9),
+		xor9 = (gray[9] ^ xor10);
+endmodule //fifo_4k_a_gray2bin_9m4
+
+
+//a_graycounter DEVICE_FAMILY="Cyclone" WIDTH=12 aclr clock cnt_en q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+//synthesis_resources = lut 13 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_a_graycounter_826
+	( 
+	aclr,
+	clock,
+	cnt_en,
+	q) /* synthesis synthesis_clearbox=1 */;
+	input   aclr;
+	input   clock;
+	input   cnt_en;
+	output   [11:0]  q;
+
+	wire  [0:0]   wire_countera_0cout;
+	wire  [0:0]   wire_countera_1cout;
+	wire  [0:0]   wire_countera_2cout;
+	wire  [0:0]   wire_countera_3cout;
+	wire  [0:0]   wire_countera_4cout;
+	wire  [0:0]   wire_countera_5cout;
+	wire  [0:0]   wire_countera_6cout;
+	wire  [0:0]   wire_countera_7cout;
+	wire  [0:0]   wire_countera_8cout;
+	wire  [0:0]   wire_countera_9cout;
+	wire  [0:0]   wire_countera_10cout;
+	wire  [11:0]   wire_countera_regout;
+	wire  wire_parity_cout;
+	wire  wire_parity_regout;
+	wire  [11:0]  power_modified_counter_values;
+	wire sclr;
+	wire updown;
+
+	cyclone_lcell   countera_0
+	( 
+	.aclr(aclr),
+	.cin(wire_parity_cout),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_0cout[0:0]),
+	.dataa(cnt_en),
+	.datab(wire_countera_regout[0:0]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[0:0]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_0.cin_used = "true",
+		countera_0.lut_mask = "c6a0",
+		countera_0.operation_mode = "arithmetic",
+		countera_0.sum_lutc_input = "cin",
+		countera_0.synch_mode = "on",
+		countera_0.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_1
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_0cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_1cout[0:0]),
+	.dataa(power_modified_counter_values[0]),
+	.datab(power_modified_counter_values[1]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[1:1]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_1.cin_used = "true",
+		countera_1.lut_mask = "6c50",
+		countera_1.operation_mode = "arithmetic",
+		countera_1.sum_lutc_input = "cin",
+		countera_1.synch_mode = "on",
+		countera_1.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_2
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_1cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_2cout[0:0]),
+	.dataa(power_modified_counter_values[1]),
+	.datab(power_modified_counter_values[2]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[2:2]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_2.cin_used = "true",
+		countera_2.lut_mask = "6c50",
+		countera_2.operation_mode = "arithmetic",
+		countera_2.sum_lutc_input = "cin",
+		countera_2.synch_mode = "on",
+		countera_2.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_3
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_2cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_3cout[0:0]),
+	.dataa(power_modified_counter_values[2]),
+	.datab(power_modified_counter_values[3]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[3:3]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_3.cin_used = "true",
+		countera_3.lut_mask = "6c50",
+		countera_3.operation_mode = "arithmetic",
+		countera_3.sum_lutc_input = "cin",
+		countera_3.synch_mode = "on",
+		countera_3.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_4
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_3cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_4cout[0:0]),
+	.dataa(power_modified_counter_values[3]),
+	.datab(power_modified_counter_values[4]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[4:4]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_4.cin_used = "true",
+		countera_4.lut_mask = "6c50",
+		countera_4.operation_mode = "arithmetic",
+		countera_4.sum_lutc_input = "cin",
+		countera_4.synch_mode = "on",
+		countera_4.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_5
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_4cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_5cout[0:0]),
+	.dataa(power_modified_counter_values[4]),
+	.datab(power_modified_counter_values[5]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[5:5]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_5.cin_used = "true",
+		countera_5.lut_mask = "6c50",
+		countera_5.operation_mode = "arithmetic",
+		countera_5.sum_lutc_input = "cin",
+		countera_5.synch_mode = "on",
+		countera_5.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_6
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_5cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_6cout[0:0]),
+	.dataa(power_modified_counter_values[5]),
+	.datab(power_modified_counter_values[6]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[6:6]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_6.cin_used = "true",
+		countera_6.lut_mask = "6c50",
+		countera_6.operation_mode = "arithmetic",
+		countera_6.sum_lutc_input = "cin",
+		countera_6.synch_mode = "on",
+		countera_6.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_7
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_6cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_7cout[0:0]),
+	.dataa(power_modified_counter_values[6]),
+	.datab(power_modified_counter_values[7]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[7:7]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_7.cin_used = "true",
+		countera_7.lut_mask = "6c50",
+		countera_7.operation_mode = "arithmetic",
+		countera_7.sum_lutc_input = "cin",
+		countera_7.synch_mode = "on",
+		countera_7.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_8
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_7cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_8cout[0:0]),
+	.dataa(power_modified_counter_values[7]),
+	.datab(power_modified_counter_values[8]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[8:8]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_8.cin_used = "true",
+		countera_8.lut_mask = "6c50",
+		countera_8.operation_mode = "arithmetic",
+		countera_8.sum_lutc_input = "cin",
+		countera_8.synch_mode = "on",
+		countera_8.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_9
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_8cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_9cout[0:0]),
+	.dataa(power_modified_counter_values[8]),
+	.datab(power_modified_counter_values[9]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[9:9]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_9.cin_used = "true",
+		countera_9.lut_mask = "6c50",
+		countera_9.operation_mode = "arithmetic",
+		countera_9.sum_lutc_input = "cin",
+		countera_9.synch_mode = "on",
+		countera_9.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_10
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_9cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_10cout[0:0]),
+	.dataa(power_modified_counter_values[9]),
+	.datab(power_modified_counter_values[10]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[10:10]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_10.cin_used = "true",
+		countera_10.lut_mask = "6c50",
+		countera_10.operation_mode = "arithmetic",
+		countera_10.sum_lutc_input = "cin",
+		countera_10.synch_mode = "on",
+		countera_10.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_11
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_10cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(),
+	.dataa(power_modified_counter_values[11]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[11:11]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datab(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_11.cin_used = "true",
+		countera_11.lut_mask = "5a5a",
+		countera_11.operation_mode = "normal",
+		countera_11.sum_lutc_input = "cin",
+		countera_11.synch_mode = "on",
+		countera_11.lpm_type = "cyclone_lcell";
+	cyclone_lcell   parity
+	( 
+	.aclr(aclr),
+	.cin(updown),
+	.clk(clock),
+	.combout(),
+	.cout(wire_parity_cout),
+	.dataa(cnt_en),
+	.datab(wire_parity_regout),
+	.ena(1'b1),
+	.regout(wire_parity_regout),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		parity.cin_used = "true",
+		parity.lut_mask = "6682",
+		parity.operation_mode = "arithmetic",
+		parity.synch_mode = "on",
+		parity.lpm_type = "cyclone_lcell";
+	assign
+		power_modified_counter_values = {wire_countera_regout[11:0]},
+		q = power_modified_counter_values,
+		sclr = 1'b0,
+		updown = 1'b1;
+endmodule //fifo_4k_a_graycounter_826
+
+
+//a_graycounter DEVICE_FAMILY="Cyclone" PVALUE=1 WIDTH=12 aclr clock cnt_en q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+//synthesis_resources = lut 13 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_a_graycounter_3r6
+	( 
+	aclr,
+	clock,
+	cnt_en,
+	q) /* synthesis synthesis_clearbox=1 */;
+	input   aclr;
+	input   clock;
+	input   cnt_en;
+	output   [11:0]  q;
+
+	wire  [0:0]   wire_countera_0cout;
+	wire  [0:0]   wire_countera_1cout;
+	wire  [0:0]   wire_countera_2cout;
+	wire  [0:0]   wire_countera_3cout;
+	wire  [0:0]   wire_countera_4cout;
+	wire  [0:0]   wire_countera_5cout;
+	wire  [0:0]   wire_countera_6cout;
+	wire  [0:0]   wire_countera_7cout;
+	wire  [0:0]   wire_countera_8cout;
+	wire  [0:0]   wire_countera_9cout;
+	wire  [0:0]   wire_countera_10cout;
+	wire  [11:0]   wire_countera_regout;
+	wire  wire_parity_cout;
+	wire  wire_parity_regout;
+	wire  [11:0]  power_modified_counter_values;
+	wire sclr;
+	wire updown;
+
+	cyclone_lcell   countera_0
+	( 
+	.aclr(aclr),
+	.cin(wire_parity_cout),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_0cout[0:0]),
+	.dataa(cnt_en),
+	.datab(wire_countera_regout[0:0]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[0:0]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_0.cin_used = "true",
+		countera_0.lut_mask = "c6a0",
+		countera_0.operation_mode = "arithmetic",
+		countera_0.sum_lutc_input = "cin",
+		countera_0.synch_mode = "on",
+		countera_0.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_1
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_0cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_1cout[0:0]),
+	.dataa(power_modified_counter_values[0]),
+	.datab(power_modified_counter_values[1]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[1:1]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_1.cin_used = "true",
+		countera_1.lut_mask = "6c50",
+		countera_1.operation_mode = "arithmetic",
+		countera_1.sum_lutc_input = "cin",
+		countera_1.synch_mode = "on",
+		countera_1.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_2
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_1cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_2cout[0:0]),
+	.dataa(power_modified_counter_values[1]),
+	.datab(power_modified_counter_values[2]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[2:2]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_2.cin_used = "true",
+		countera_2.lut_mask = "6c50",
+		countera_2.operation_mode = "arithmetic",
+		countera_2.sum_lutc_input = "cin",
+		countera_2.synch_mode = "on",
+		countera_2.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_3
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_2cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_3cout[0:0]),
+	.dataa(power_modified_counter_values[2]),
+	.datab(power_modified_counter_values[3]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[3:3]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_3.cin_used = "true",
+		countera_3.lut_mask = "6c50",
+		countera_3.operation_mode = "arithmetic",
+		countera_3.sum_lutc_input = "cin",
+		countera_3.synch_mode = "on",
+		countera_3.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_4
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_3cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_4cout[0:0]),
+	.dataa(power_modified_counter_values[3]),
+	.datab(power_modified_counter_values[4]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[4:4]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_4.cin_used = "true",
+		countera_4.lut_mask = "6c50",
+		countera_4.operation_mode = "arithmetic",
+		countera_4.sum_lutc_input = "cin",
+		countera_4.synch_mode = "on",
+		countera_4.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_5
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_4cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_5cout[0:0]),
+	.dataa(power_modified_counter_values[4]),
+	.datab(power_modified_counter_values[5]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[5:5]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_5.cin_used = "true",
+		countera_5.lut_mask = "6c50",
+		countera_5.operation_mode = "arithmetic",
+		countera_5.sum_lutc_input = "cin",
+		countera_5.synch_mode = "on",
+		countera_5.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_6
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_5cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_6cout[0:0]),
+	.dataa(power_modified_counter_values[5]),
+	.datab(power_modified_counter_values[6]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[6:6]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_6.cin_used = "true",
+		countera_6.lut_mask = "6c50",
+		countera_6.operation_mode = "arithmetic",
+		countera_6.sum_lutc_input = "cin",
+		countera_6.synch_mode = "on",
+		countera_6.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_7
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_6cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_7cout[0:0]),
+	.dataa(power_modified_counter_values[6]),
+	.datab(power_modified_counter_values[7]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[7:7]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_7.cin_used = "true",
+		countera_7.lut_mask = "6c50",
+		countera_7.operation_mode = "arithmetic",
+		countera_7.sum_lutc_input = "cin",
+		countera_7.synch_mode = "on",
+		countera_7.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_8
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_7cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_8cout[0:0]),
+	.dataa(power_modified_counter_values[7]),
+	.datab(power_modified_counter_values[8]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[8:8]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_8.cin_used = "true",
+		countera_8.lut_mask = "6c50",
+		countera_8.operation_mode = "arithmetic",
+		countera_8.sum_lutc_input = "cin",
+		countera_8.synch_mode = "on",
+		countera_8.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_9
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_8cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_9cout[0:0]),
+	.dataa(power_modified_counter_values[8]),
+	.datab(power_modified_counter_values[9]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[9:9]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_9.cin_used = "true",
+		countera_9.lut_mask = "6c50",
+		countera_9.operation_mode = "arithmetic",
+		countera_9.sum_lutc_input = "cin",
+		countera_9.synch_mode = "on",
+		countera_9.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_10
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_9cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(wire_countera_10cout[0:0]),
+	.dataa(power_modified_counter_values[9]),
+	.datab(power_modified_counter_values[10]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[10:10]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_10.cin_used = "true",
+		countera_10.lut_mask = "6c50",
+		countera_10.operation_mode = "arithmetic",
+		countera_10.sum_lutc_input = "cin",
+		countera_10.synch_mode = "on",
+		countera_10.lpm_type = "cyclone_lcell";
+	cyclone_lcell   countera_11
+	( 
+	.aclr(aclr),
+	.cin(wire_countera_10cout[0:0]),
+	.clk(clock),
+	.combout(),
+	.cout(),
+	.dataa(power_modified_counter_values[11]),
+	.ena(1'b1),
+	.regout(wire_countera_regout[11:11]),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datab(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		countera_11.cin_used = "true",
+		countera_11.lut_mask = "5a5a",
+		countera_11.operation_mode = "normal",
+		countera_11.sum_lutc_input = "cin",
+		countera_11.synch_mode = "on",
+		countera_11.lpm_type = "cyclone_lcell";
+	cyclone_lcell   parity
+	( 
+	.aclr(aclr),
+	.cin(updown),
+	.clk(clock),
+	.combout(),
+	.cout(wire_parity_cout),
+	.dataa(cnt_en),
+	.datab((~ wire_parity_regout)),
+	.ena(1'b1),
+	.regout(wire_parity_regout),
+	.sclr(sclr)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aload(1'b0),
+	.datac(1'b1),
+	.datad(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		parity.cin_used = "true",
+		parity.lut_mask = "9982",
+		parity.operation_mode = "arithmetic",
+		parity.synch_mode = "on",
+		parity.lpm_type = "cyclone_lcell";
+	assign
+		power_modified_counter_values = {wire_countera_regout[11:1], (~ wire_countera_regout[0])},
+		q = power_modified_counter_values,
+		sclr = 1'b0,
+		updown = 1'b1;
+endmodule //fifo_4k_a_graycounter_3r6
+
+
+//altsyncram ADDRESS_REG_B="CLOCK1" DEVICE_FAMILY="Cyclone" OPERATION_MODE="DUAL_PORT" OUTDATA_REG_B="UNREGISTERED" WIDTH_A=16 WIDTH_B=16 WIDTH_BYTEENA_A=1 WIDTHAD_A=12 WIDTHAD_B=12 address_a address_b clock0 clock1 clocken1 data_a q_b wren_a
+//VERSION_BEGIN 5.0 cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+//synthesis_resources = M4K 16 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_altsyncram_8pl
+	( 
+	address_a,
+	address_b,
+	clock0,
+	clock1,
+	clocken1,
+	data_a,
+	q_b,
+	wren_a) /* synthesis synthesis_clearbox=1 */;
+	input   [11:0]  address_a;
+	input   [11:0]  address_b;
+	input   clock0;
+	input   clock1;
+	input   clocken1;
+	input   [15:0]  data_a;
+	output   [15:0]  q_b;
+	input   wren_a;
+
+	wire  [0:0]   wire_ram_block3a_0portbdataout;
+	wire  [0:0]   wire_ram_block3a_1portbdataout;
+	wire  [0:0]   wire_ram_block3a_2portbdataout;
+	wire  [0:0]   wire_ram_block3a_3portbdataout;
+	wire  [0:0]   wire_ram_block3a_4portbdataout;
+	wire  [0:0]   wire_ram_block3a_5portbdataout;
+	wire  [0:0]   wire_ram_block3a_6portbdataout;
+	wire  [0:0]   wire_ram_block3a_7portbdataout;
+	wire  [0:0]   wire_ram_block3a_8portbdataout;
+	wire  [0:0]   wire_ram_block3a_9portbdataout;
+	wire  [0:0]   wire_ram_block3a_10portbdataout;
+	wire  [0:0]   wire_ram_block3a_11portbdataout;
+	wire  [0:0]   wire_ram_block3a_12portbdataout;
+	wire  [0:0]   wire_ram_block3a_13portbdataout;
+	wire  [0:0]   wire_ram_block3a_14portbdataout;
+	wire  [0:0]   wire_ram_block3a_15portbdataout;
+	wire  [11:0]  address_a_wire;
+	wire  [11:0]  address_b_wire;
+
+	cyclone_ram_block   ram_block3a_0
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[0]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_0portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_0.connectivity_checking = "OFF",
+		ram_block3a_0.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_0.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_0.operation_mode = "dual_port",
+		ram_block3a_0.port_a_address_width = 12,
+		ram_block3a_0.port_a_data_width = 1,
+		ram_block3a_0.port_a_first_address = 0,
+		ram_block3a_0.port_a_first_bit_number = 0,
+		ram_block3a_0.port_a_last_address = 4095,
+		ram_block3a_0.port_a_logical_ram_depth = 4096,
+		ram_block3a_0.port_a_logical_ram_width = 16,
+		ram_block3a_0.port_b_address_clear = "none",
+		ram_block3a_0.port_b_address_clock = "clock1",
+		ram_block3a_0.port_b_address_width = 12,
+		ram_block3a_0.port_b_data_out_clear = "none",
+		ram_block3a_0.port_b_data_out_clock = "none",
+		ram_block3a_0.port_b_data_width = 1,
+		ram_block3a_0.port_b_first_address = 0,
+		ram_block3a_0.port_b_first_bit_number = 0,
+		ram_block3a_0.port_b_last_address = 4095,
+		ram_block3a_0.port_b_logical_ram_depth = 4096,
+		ram_block3a_0.port_b_logical_ram_width = 16,
+		ram_block3a_0.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_0.ram_block_type = "auto",
+		ram_block3a_0.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_1
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[1]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_1portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_1.connectivity_checking = "OFF",
+		ram_block3a_1.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_1.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_1.operation_mode = "dual_port",
+		ram_block3a_1.port_a_address_width = 12,
+		ram_block3a_1.port_a_data_width = 1,
+		ram_block3a_1.port_a_first_address = 0,
+		ram_block3a_1.port_a_first_bit_number = 1,
+		ram_block3a_1.port_a_last_address = 4095,
+		ram_block3a_1.port_a_logical_ram_depth = 4096,
+		ram_block3a_1.port_a_logical_ram_width = 16,
+		ram_block3a_1.port_b_address_clear = "none",
+		ram_block3a_1.port_b_address_clock = "clock1",
+		ram_block3a_1.port_b_address_width = 12,
+		ram_block3a_1.port_b_data_out_clear = "none",
+		ram_block3a_1.port_b_data_out_clock = "none",
+		ram_block3a_1.port_b_data_width = 1,
+		ram_block3a_1.port_b_first_address = 0,
+		ram_block3a_1.port_b_first_bit_number = 1,
+		ram_block3a_1.port_b_last_address = 4095,
+		ram_block3a_1.port_b_logical_ram_depth = 4096,
+		ram_block3a_1.port_b_logical_ram_width = 16,
+		ram_block3a_1.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_1.ram_block_type = "auto",
+		ram_block3a_1.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_2
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[2]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_2portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_2.connectivity_checking = "OFF",
+		ram_block3a_2.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_2.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_2.operation_mode = "dual_port",
+		ram_block3a_2.port_a_address_width = 12,
+		ram_block3a_2.port_a_data_width = 1,
+		ram_block3a_2.port_a_first_address = 0,
+		ram_block3a_2.port_a_first_bit_number = 2,
+		ram_block3a_2.port_a_last_address = 4095,
+		ram_block3a_2.port_a_logical_ram_depth = 4096,
+		ram_block3a_2.port_a_logical_ram_width = 16,
+		ram_block3a_2.port_b_address_clear = "none",
+		ram_block3a_2.port_b_address_clock = "clock1",
+		ram_block3a_2.port_b_address_width = 12,
+		ram_block3a_2.port_b_data_out_clear = "none",
+		ram_block3a_2.port_b_data_out_clock = "none",
+		ram_block3a_2.port_b_data_width = 1,
+		ram_block3a_2.port_b_first_address = 0,
+		ram_block3a_2.port_b_first_bit_number = 2,
+		ram_block3a_2.port_b_last_address = 4095,
+		ram_block3a_2.port_b_logical_ram_depth = 4096,
+		ram_block3a_2.port_b_logical_ram_width = 16,
+		ram_block3a_2.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_2.ram_block_type = "auto",
+		ram_block3a_2.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_3
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[3]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_3portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_3.connectivity_checking = "OFF",
+		ram_block3a_3.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_3.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_3.operation_mode = "dual_port",
+		ram_block3a_3.port_a_address_width = 12,
+		ram_block3a_3.port_a_data_width = 1,
+		ram_block3a_3.port_a_first_address = 0,
+		ram_block3a_3.port_a_first_bit_number = 3,
+		ram_block3a_3.port_a_last_address = 4095,
+		ram_block3a_3.port_a_logical_ram_depth = 4096,
+		ram_block3a_3.port_a_logical_ram_width = 16,
+		ram_block3a_3.port_b_address_clear = "none",
+		ram_block3a_3.port_b_address_clock = "clock1",
+		ram_block3a_3.port_b_address_width = 12,
+		ram_block3a_3.port_b_data_out_clear = "none",
+		ram_block3a_3.port_b_data_out_clock = "none",
+		ram_block3a_3.port_b_data_width = 1,
+		ram_block3a_3.port_b_first_address = 0,
+		ram_block3a_3.port_b_first_bit_number = 3,
+		ram_block3a_3.port_b_last_address = 4095,
+		ram_block3a_3.port_b_logical_ram_depth = 4096,
+		ram_block3a_3.port_b_logical_ram_width = 16,
+		ram_block3a_3.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_3.ram_block_type = "auto",
+		ram_block3a_3.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_4
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[4]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_4portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_4.connectivity_checking = "OFF",
+		ram_block3a_4.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_4.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_4.operation_mode = "dual_port",
+		ram_block3a_4.port_a_address_width = 12,
+		ram_block3a_4.port_a_data_width = 1,
+		ram_block3a_4.port_a_first_address = 0,
+		ram_block3a_4.port_a_first_bit_number = 4,
+		ram_block3a_4.port_a_last_address = 4095,
+		ram_block3a_4.port_a_logical_ram_depth = 4096,
+		ram_block3a_4.port_a_logical_ram_width = 16,
+		ram_block3a_4.port_b_address_clear = "none",
+		ram_block3a_4.port_b_address_clock = "clock1",
+		ram_block3a_4.port_b_address_width = 12,
+		ram_block3a_4.port_b_data_out_clear = "none",
+		ram_block3a_4.port_b_data_out_clock = "none",
+		ram_block3a_4.port_b_data_width = 1,
+		ram_block3a_4.port_b_first_address = 0,
+		ram_block3a_4.port_b_first_bit_number = 4,
+		ram_block3a_4.port_b_last_address = 4095,
+		ram_block3a_4.port_b_logical_ram_depth = 4096,
+		ram_block3a_4.port_b_logical_ram_width = 16,
+		ram_block3a_4.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_4.ram_block_type = "auto",
+		ram_block3a_4.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_5
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[5]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_5portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_5.connectivity_checking = "OFF",
+		ram_block3a_5.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_5.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_5.operation_mode = "dual_port",
+		ram_block3a_5.port_a_address_width = 12,
+		ram_block3a_5.port_a_data_width = 1,
+		ram_block3a_5.port_a_first_address = 0,
+		ram_block3a_5.port_a_first_bit_number = 5,
+		ram_block3a_5.port_a_last_address = 4095,
+		ram_block3a_5.port_a_logical_ram_depth = 4096,
+		ram_block3a_5.port_a_logical_ram_width = 16,
+		ram_block3a_5.port_b_address_clear = "none",
+		ram_block3a_5.port_b_address_clock = "clock1",
+		ram_block3a_5.port_b_address_width = 12,
+		ram_block3a_5.port_b_data_out_clear = "none",
+		ram_block3a_5.port_b_data_out_clock = "none",
+		ram_block3a_5.port_b_data_width = 1,
+		ram_block3a_5.port_b_first_address = 0,
+		ram_block3a_5.port_b_first_bit_number = 5,
+		ram_block3a_5.port_b_last_address = 4095,
+		ram_block3a_5.port_b_logical_ram_depth = 4096,
+		ram_block3a_5.port_b_logical_ram_width = 16,
+		ram_block3a_5.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_5.ram_block_type = "auto",
+		ram_block3a_5.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_6
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[6]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_6portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_6.connectivity_checking = "OFF",
+		ram_block3a_6.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_6.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_6.operation_mode = "dual_port",
+		ram_block3a_6.port_a_address_width = 12,
+		ram_block3a_6.port_a_data_width = 1,
+		ram_block3a_6.port_a_first_address = 0,
+		ram_block3a_6.port_a_first_bit_number = 6,
+		ram_block3a_6.port_a_last_address = 4095,
+		ram_block3a_6.port_a_logical_ram_depth = 4096,
+		ram_block3a_6.port_a_logical_ram_width = 16,
+		ram_block3a_6.port_b_address_clear = "none",
+		ram_block3a_6.port_b_address_clock = "clock1",
+		ram_block3a_6.port_b_address_width = 12,
+		ram_block3a_6.port_b_data_out_clear = "none",
+		ram_block3a_6.port_b_data_out_clock = "none",
+		ram_block3a_6.port_b_data_width = 1,
+		ram_block3a_6.port_b_first_address = 0,
+		ram_block3a_6.port_b_first_bit_number = 6,
+		ram_block3a_6.port_b_last_address = 4095,
+		ram_block3a_6.port_b_logical_ram_depth = 4096,
+		ram_block3a_6.port_b_logical_ram_width = 16,
+		ram_block3a_6.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_6.ram_block_type = "auto",
+		ram_block3a_6.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_7
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[7]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_7portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_7.connectivity_checking = "OFF",
+		ram_block3a_7.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_7.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_7.operation_mode = "dual_port",
+		ram_block3a_7.port_a_address_width = 12,
+		ram_block3a_7.port_a_data_width = 1,
+		ram_block3a_7.port_a_first_address = 0,
+		ram_block3a_7.port_a_first_bit_number = 7,
+		ram_block3a_7.port_a_last_address = 4095,
+		ram_block3a_7.port_a_logical_ram_depth = 4096,
+		ram_block3a_7.port_a_logical_ram_width = 16,
+		ram_block3a_7.port_b_address_clear = "none",
+		ram_block3a_7.port_b_address_clock = "clock1",
+		ram_block3a_7.port_b_address_width = 12,
+		ram_block3a_7.port_b_data_out_clear = "none",
+		ram_block3a_7.port_b_data_out_clock = "none",
+		ram_block3a_7.port_b_data_width = 1,
+		ram_block3a_7.port_b_first_address = 0,
+		ram_block3a_7.port_b_first_bit_number = 7,
+		ram_block3a_7.port_b_last_address = 4095,
+		ram_block3a_7.port_b_logical_ram_depth = 4096,
+		ram_block3a_7.port_b_logical_ram_width = 16,
+		ram_block3a_7.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_7.ram_block_type = "auto",
+		ram_block3a_7.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_8
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[8]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_8portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_8.connectivity_checking = "OFF",
+		ram_block3a_8.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_8.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_8.operation_mode = "dual_port",
+		ram_block3a_8.port_a_address_width = 12,
+		ram_block3a_8.port_a_data_width = 1,
+		ram_block3a_8.port_a_first_address = 0,
+		ram_block3a_8.port_a_first_bit_number = 8,
+		ram_block3a_8.port_a_last_address = 4095,
+		ram_block3a_8.port_a_logical_ram_depth = 4096,
+		ram_block3a_8.port_a_logical_ram_width = 16,
+		ram_block3a_8.port_b_address_clear = "none",
+		ram_block3a_8.port_b_address_clock = "clock1",
+		ram_block3a_8.port_b_address_width = 12,
+		ram_block3a_8.port_b_data_out_clear = "none",
+		ram_block3a_8.port_b_data_out_clock = "none",
+		ram_block3a_8.port_b_data_width = 1,
+		ram_block3a_8.port_b_first_address = 0,
+		ram_block3a_8.port_b_first_bit_number = 8,
+		ram_block3a_8.port_b_last_address = 4095,
+		ram_block3a_8.port_b_logical_ram_depth = 4096,
+		ram_block3a_8.port_b_logical_ram_width = 16,
+		ram_block3a_8.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_8.ram_block_type = "auto",
+		ram_block3a_8.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_9
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[9]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_9portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_9.connectivity_checking = "OFF",
+		ram_block3a_9.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_9.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_9.operation_mode = "dual_port",
+		ram_block3a_9.port_a_address_width = 12,
+		ram_block3a_9.port_a_data_width = 1,
+		ram_block3a_9.port_a_first_address = 0,
+		ram_block3a_9.port_a_first_bit_number = 9,
+		ram_block3a_9.port_a_last_address = 4095,
+		ram_block3a_9.port_a_logical_ram_depth = 4096,
+		ram_block3a_9.port_a_logical_ram_width = 16,
+		ram_block3a_9.port_b_address_clear = "none",
+		ram_block3a_9.port_b_address_clock = "clock1",
+		ram_block3a_9.port_b_address_width = 12,
+		ram_block3a_9.port_b_data_out_clear = "none",
+		ram_block3a_9.port_b_data_out_clock = "none",
+		ram_block3a_9.port_b_data_width = 1,
+		ram_block3a_9.port_b_first_address = 0,
+		ram_block3a_9.port_b_first_bit_number = 9,
+		ram_block3a_9.port_b_last_address = 4095,
+		ram_block3a_9.port_b_logical_ram_depth = 4096,
+		ram_block3a_9.port_b_logical_ram_width = 16,
+		ram_block3a_9.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_9.ram_block_type = "auto",
+		ram_block3a_9.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_10
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[10]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_10portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_10.connectivity_checking = "OFF",
+		ram_block3a_10.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_10.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_10.operation_mode = "dual_port",
+		ram_block3a_10.port_a_address_width = 12,
+		ram_block3a_10.port_a_data_width = 1,
+		ram_block3a_10.port_a_first_address = 0,
+		ram_block3a_10.port_a_first_bit_number = 10,
+		ram_block3a_10.port_a_last_address = 4095,
+		ram_block3a_10.port_a_logical_ram_depth = 4096,
+		ram_block3a_10.port_a_logical_ram_width = 16,
+		ram_block3a_10.port_b_address_clear = "none",
+		ram_block3a_10.port_b_address_clock = "clock1",
+		ram_block3a_10.port_b_address_width = 12,
+		ram_block3a_10.port_b_data_out_clear = "none",
+		ram_block3a_10.port_b_data_out_clock = "none",
+		ram_block3a_10.port_b_data_width = 1,
+		ram_block3a_10.port_b_first_address = 0,
+		ram_block3a_10.port_b_first_bit_number = 10,
+		ram_block3a_10.port_b_last_address = 4095,
+		ram_block3a_10.port_b_logical_ram_depth = 4096,
+		ram_block3a_10.port_b_logical_ram_width = 16,
+		ram_block3a_10.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_10.ram_block_type = "auto",
+		ram_block3a_10.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_11
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[11]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_11portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_11.connectivity_checking = "OFF",
+		ram_block3a_11.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_11.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_11.operation_mode = "dual_port",
+		ram_block3a_11.port_a_address_width = 12,
+		ram_block3a_11.port_a_data_width = 1,
+		ram_block3a_11.port_a_first_address = 0,
+		ram_block3a_11.port_a_first_bit_number = 11,
+		ram_block3a_11.port_a_last_address = 4095,
+		ram_block3a_11.port_a_logical_ram_depth = 4096,
+		ram_block3a_11.port_a_logical_ram_width = 16,
+		ram_block3a_11.port_b_address_clear = "none",
+		ram_block3a_11.port_b_address_clock = "clock1",
+		ram_block3a_11.port_b_address_width = 12,
+		ram_block3a_11.port_b_data_out_clear = "none",
+		ram_block3a_11.port_b_data_out_clock = "none",
+		ram_block3a_11.port_b_data_width = 1,
+		ram_block3a_11.port_b_first_address = 0,
+		ram_block3a_11.port_b_first_bit_number = 11,
+		ram_block3a_11.port_b_last_address = 4095,
+		ram_block3a_11.port_b_logical_ram_depth = 4096,
+		ram_block3a_11.port_b_logical_ram_width = 16,
+		ram_block3a_11.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_11.ram_block_type = "auto",
+		ram_block3a_11.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_12
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[12]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_12portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_12.connectivity_checking = "OFF",
+		ram_block3a_12.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_12.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_12.operation_mode = "dual_port",
+		ram_block3a_12.port_a_address_width = 12,
+		ram_block3a_12.port_a_data_width = 1,
+		ram_block3a_12.port_a_first_address = 0,
+		ram_block3a_12.port_a_first_bit_number = 12,
+		ram_block3a_12.port_a_last_address = 4095,
+		ram_block3a_12.port_a_logical_ram_depth = 4096,
+		ram_block3a_12.port_a_logical_ram_width = 16,
+		ram_block3a_12.port_b_address_clear = "none",
+		ram_block3a_12.port_b_address_clock = "clock1",
+		ram_block3a_12.port_b_address_width = 12,
+		ram_block3a_12.port_b_data_out_clear = "none",
+		ram_block3a_12.port_b_data_out_clock = "none",
+		ram_block3a_12.port_b_data_width = 1,
+		ram_block3a_12.port_b_first_address = 0,
+		ram_block3a_12.port_b_first_bit_number = 12,
+		ram_block3a_12.port_b_last_address = 4095,
+		ram_block3a_12.port_b_logical_ram_depth = 4096,
+		ram_block3a_12.port_b_logical_ram_width = 16,
+		ram_block3a_12.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_12.ram_block_type = "auto",
+		ram_block3a_12.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_13
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[13]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_13portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_13.connectivity_checking = "OFF",
+		ram_block3a_13.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_13.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_13.operation_mode = "dual_port",
+		ram_block3a_13.port_a_address_width = 12,
+		ram_block3a_13.port_a_data_width = 1,
+		ram_block3a_13.port_a_first_address = 0,
+		ram_block3a_13.port_a_first_bit_number = 13,
+		ram_block3a_13.port_a_last_address = 4095,
+		ram_block3a_13.port_a_logical_ram_depth = 4096,
+		ram_block3a_13.port_a_logical_ram_width = 16,
+		ram_block3a_13.port_b_address_clear = "none",
+		ram_block3a_13.port_b_address_clock = "clock1",
+		ram_block3a_13.port_b_address_width = 12,
+		ram_block3a_13.port_b_data_out_clear = "none",
+		ram_block3a_13.port_b_data_out_clock = "none",
+		ram_block3a_13.port_b_data_width = 1,
+		ram_block3a_13.port_b_first_address = 0,
+		ram_block3a_13.port_b_first_bit_number = 13,
+		ram_block3a_13.port_b_last_address = 4095,
+		ram_block3a_13.port_b_logical_ram_depth = 4096,
+		ram_block3a_13.port_b_logical_ram_width = 16,
+		ram_block3a_13.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_13.ram_block_type = "auto",
+		ram_block3a_13.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_14
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[14]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_14portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_14.connectivity_checking = "OFF",
+		ram_block3a_14.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_14.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_14.operation_mode = "dual_port",
+		ram_block3a_14.port_a_address_width = 12,
+		ram_block3a_14.port_a_data_width = 1,
+		ram_block3a_14.port_a_first_address = 0,
+		ram_block3a_14.port_a_first_bit_number = 14,
+		ram_block3a_14.port_a_last_address = 4095,
+		ram_block3a_14.port_a_logical_ram_depth = 4096,
+		ram_block3a_14.port_a_logical_ram_width = 16,
+		ram_block3a_14.port_b_address_clear = "none",
+		ram_block3a_14.port_b_address_clock = "clock1",
+		ram_block3a_14.port_b_address_width = 12,
+		ram_block3a_14.port_b_data_out_clear = "none",
+		ram_block3a_14.port_b_data_out_clock = "none",
+		ram_block3a_14.port_b_data_width = 1,
+		ram_block3a_14.port_b_first_address = 0,
+		ram_block3a_14.port_b_first_bit_number = 14,
+		ram_block3a_14.port_b_last_address = 4095,
+		ram_block3a_14.port_b_logical_ram_depth = 4096,
+		ram_block3a_14.port_b_logical_ram_width = 16,
+		ram_block3a_14.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_14.ram_block_type = "auto",
+		ram_block3a_14.lpm_type = "cyclone_ram_block";
+	cyclone_ram_block   ram_block3a_15
+	( 
+	.clk0(clock0),
+	.clk1(clock1),
+	.ena0(wren_a),
+	.ena1(clocken1),
+	.portaaddr({address_a_wire[11:0]}),
+	.portadatain({data_a[15]}),
+	.portadataout(),
+	.portawe(1'b1),
+	.portbaddr({address_b_wire[11:0]}),
+	.portbdataout(wire_ram_block3a_15portbdataout[0:0]),
+	.portbrewe(1'b1)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.clr0(1'b0),
+	.clr1(1'b0),
+	.portabyteenamasks(1'b1),
+	.portbbyteenamasks(1'b1),
+	.portbdatain(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		ram_block3a_15.connectivity_checking = "OFF",
+		ram_block3a_15.logical_ram_name = "ALTSYNCRAM",
+		ram_block3a_15.mixed_port_feed_through_mode = "dont_care",
+		ram_block3a_15.operation_mode = "dual_port",
+		ram_block3a_15.port_a_address_width = 12,
+		ram_block3a_15.port_a_data_width = 1,
+		ram_block3a_15.port_a_first_address = 0,
+		ram_block3a_15.port_a_first_bit_number = 15,
+		ram_block3a_15.port_a_last_address = 4095,
+		ram_block3a_15.port_a_logical_ram_depth = 4096,
+		ram_block3a_15.port_a_logical_ram_width = 16,
+		ram_block3a_15.port_b_address_clear = "none",
+		ram_block3a_15.port_b_address_clock = "clock1",
+		ram_block3a_15.port_b_address_width = 12,
+		ram_block3a_15.port_b_data_out_clear = "none",
+		ram_block3a_15.port_b_data_out_clock = "none",
+		ram_block3a_15.port_b_data_width = 1,
+		ram_block3a_15.port_b_first_address = 0,
+		ram_block3a_15.port_b_first_bit_number = 15,
+		ram_block3a_15.port_b_last_address = 4095,
+		ram_block3a_15.port_b_logical_ram_depth = 4096,
+		ram_block3a_15.port_b_logical_ram_width = 16,
+		ram_block3a_15.port_b_read_enable_write_enable_clock = "clock1",
+		ram_block3a_15.ram_block_type = "auto",
+		ram_block3a_15.lpm_type = "cyclone_ram_block";
+	assign
+		address_a_wire = address_a,
+		address_b_wire = address_b,
+		q_b = {wire_ram_block3a_15portbdataout[0], wire_ram_block3a_14portbdataout[0], wire_ram_block3a_13portbdataout[0], wire_ram_block3a_12portbdataout[0], wire_ram_block3a_11portbdataout[0], wire_ram_block3a_10portbdataout[0], wire_ram_block3a_9portbdataout[0], wire_ram_block3a_8portbdataout[0], wire_ram_block3a_7portbdataout[0], wire_ram_block3a_6portbdataout[0], wire_ram_block3a_5portbdataout[0], wire_ram_block3a_4portbdataout[0], wire_ram_block3a_3portbdataout[0], wire_ram_block3a_2portbdataout[0], wire_ram_block3a_1portbdataout[0], wire_ram_block3a_0portbdataout[0]};
+endmodule //fifo_4k_altsyncram_8pl
+
+
+//dffpipe DELAY=1 WIDTH=12 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+//synthesis_resources = lut 12 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_dffpipe_bb3
+	( 
+	clock,
+	clrn,
+	d,
+	q) /* synthesis synthesis_clearbox=1 */
+		/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
+	input   clock;
+	input   clrn;
+	input   [11:0]  d;
+	output   [11:0]  q;
+
+	wire	[11:0]	wire_dffe4a_D;
+	reg	[11:0]	dffe4a;
+	wire ena;
+	wire prn;
+	wire sclr;
+
+	// synopsys translate_off
+	initial
+		dffe4a[0:0] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a[0:0] <= 1'b1;
+		else if (clrn == 1'b0) dffe4a[0:0] <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a[0:0] <= wire_dffe4a_D[0:0];
+	// synopsys translate_off
+	initial
+		dffe4a[1:1] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a[1:1] <= 1'b1;
+		else if (clrn == 1'b0) dffe4a[1:1] <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a[1:1] <= wire_dffe4a_D[1:1];
+	// synopsys translate_off
+	initial
+		dffe4a[2:2] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a[2:2] <= 1'b1;
+		else if (clrn == 1'b0) dffe4a[2:2] <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a[2:2] <= wire_dffe4a_D[2:2];
+	// synopsys translate_off
+	initial
+		dffe4a[3:3] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a[3:3] <= 1'b1;
+		else if (clrn == 1'b0) dffe4a[3:3] <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a[3:3] <= wire_dffe4a_D[3:3];
+	// synopsys translate_off
+	initial
+		dffe4a[4:4] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a[4:4] <= 1'b1;
+		else if (clrn == 1'b0) dffe4a[4:4] <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a[4:4] <= wire_dffe4a_D[4:4];
+	// synopsys translate_off
+	initial
+		dffe4a[5:5] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a[5:5] <= 1'b1;
+		else if (clrn == 1'b0) dffe4a[5:5] <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a[5:5] <= wire_dffe4a_D[5:5];
+	// synopsys translate_off
+	initial
+		dffe4a[6:6] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a[6:6] <= 1'b1;
+		else if (clrn == 1'b0) dffe4a[6:6] <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a[6:6] <= wire_dffe4a_D[6:6];
+	// synopsys translate_off
+	initial
+		dffe4a[7:7] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a[7:7] <= 1'b1;
+		else if (clrn == 1'b0) dffe4a[7:7] <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a[7:7] <= wire_dffe4a_D[7:7];
+	// synopsys translate_off
+	initial
+		dffe4a[8:8] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a[8:8] <= 1'b1;
+		else if (clrn == 1'b0) dffe4a[8:8] <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a[8:8] <= wire_dffe4a_D[8:8];
+	// synopsys translate_off
+	initial
+		dffe4a[9:9] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a[9:9] <= 1'b1;
+		else if (clrn == 1'b0) dffe4a[9:9] <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a[9:9] <= wire_dffe4a_D[9:9];
+	// synopsys translate_off
+	initial
+		dffe4a[10:10] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a[10:10] <= 1'b1;
+		else if (clrn == 1'b0) dffe4a[10:10] <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a[10:10] <= wire_dffe4a_D[10:10];
+	// synopsys translate_off
+	initial
+		dffe4a[11:11] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe4a[11:11] <= 1'b1;
+		else if (clrn == 1'b0) dffe4a[11:11] <= 1'b0;
+		else if  (ena == 1'b1)   dffe4a[11:11] <= wire_dffe4a_D[11:11];
+	assign
+		wire_dffe4a_D = (d & {12{(~ sclr)}});
+	assign
+		ena = 1'b1,
+		prn = 1'b1,
+		q = dffe4a,
+		sclr = 1'b0;
+endmodule //fifo_4k_dffpipe_bb3
+
+
+//dffpipe WIDTH=12 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_a_gray2bin 2004:03:06:00:52:20:SJ cbx_a_graycounter 2004:10:01:12:13:16:SJ cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:03:24:13:58:56:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_dcfifo 2005:03:07:17:11:14:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_flex10ke 2002:10:18:16:54:38:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+
+//dffpipe WIDTH=12 clock clrn d q
+//VERSION_BEGIN 5.0 cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END
+
+//synthesis_resources = lut 12 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_dffpipe_em2
+	( 
+	clock,
+	clrn,
+	d,
+	q) /* synthesis synthesis_clearbox=1 */
+		/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF" */;
+	input   clock;
+	input   clrn;
+	input   [11:0]  d;
+	output   [11:0]  q;
+
+	wire	[11:0]	wire_dffe6a_D;
+	reg	[11:0]	dffe6a;
+	wire ena;
+	wire prn;
+	wire sclr;
+
+	// synopsys translate_off
+	initial
+		dffe6a[0:0] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a[0:0] <= 1'b1;
+		else if (clrn == 1'b0) dffe6a[0:0] <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a[0:0] <= wire_dffe6a_D[0:0];
+	// synopsys translate_off
+	initial
+		dffe6a[1:1] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a[1:1] <= 1'b1;
+		else if (clrn == 1'b0) dffe6a[1:1] <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a[1:1] <= wire_dffe6a_D[1:1];
+	// synopsys translate_off
+	initial
+		dffe6a[2:2] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a[2:2] <= 1'b1;
+		else if (clrn == 1'b0) dffe6a[2:2] <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a[2:2] <= wire_dffe6a_D[2:2];
+	// synopsys translate_off
+	initial
+		dffe6a[3:3] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a[3:3] <= 1'b1;
+		else if (clrn == 1'b0) dffe6a[3:3] <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a[3:3] <= wire_dffe6a_D[3:3];
+	// synopsys translate_off
+	initial
+		dffe6a[4:4] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a[4:4] <= 1'b1;
+		else if (clrn == 1'b0) dffe6a[4:4] <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a[4:4] <= wire_dffe6a_D[4:4];
+	// synopsys translate_off
+	initial
+		dffe6a[5:5] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a[5:5] <= 1'b1;
+		else if (clrn == 1'b0) dffe6a[5:5] <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a[5:5] <= wire_dffe6a_D[5:5];
+	// synopsys translate_off
+	initial
+		dffe6a[6:6] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a[6:6] <= 1'b1;
+		else if (clrn == 1'b0) dffe6a[6:6] <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a[6:6] <= wire_dffe6a_D[6:6];
+	// synopsys translate_off
+	initial
+		dffe6a[7:7] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a[7:7] <= 1'b1;
+		else if (clrn == 1'b0) dffe6a[7:7] <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a[7:7] <= wire_dffe6a_D[7:7];
+	// synopsys translate_off
+	initial
+		dffe6a[8:8] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a[8:8] <= 1'b1;
+		else if (clrn == 1'b0) dffe6a[8:8] <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a[8:8] <= wire_dffe6a_D[8:8];
+	// synopsys translate_off
+	initial
+		dffe6a[9:9] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a[9:9] <= 1'b1;
+		else if (clrn == 1'b0) dffe6a[9:9] <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a[9:9] <= wire_dffe6a_D[9:9];
+	// synopsys translate_off
+	initial
+		dffe6a[10:10] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a[10:10] <= 1'b1;
+		else if (clrn == 1'b0) dffe6a[10:10] <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a[10:10] <= wire_dffe6a_D[10:10];
+	// synopsys translate_off
+	initial
+		dffe6a[11:11] = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  negedge prn or  negedge clrn)
+		if (prn == 1'b0) dffe6a[11:11] <= 1'b1;
+		else if (clrn == 1'b0) dffe6a[11:11] <= 1'b0;
+		else if  (ena == 1'b1)   dffe6a[11:11] <= wire_dffe6a_D[11:11];
+	assign
+		wire_dffe6a_D = (d & {12{(~ sclr)}});
+	assign
+		ena = 1'b1,
+		prn = 1'b1,
+		q = dffe6a,
+		sclr = 1'b0;
+endmodule //fifo_4k_dffpipe_em2
+
+//synthesis_resources = lut 12 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_alt_synch_pipe_em2
+	( 
+	clock,
+	clrn,
+	d,
+	q) /* synthesis synthesis_clearbox=1 */
+		/* synthesis ALTERA_ATTRIBUTE="X_ON_VIOLATION_OPTION=OFF" */;
+	input   clock;
+	input   clrn;
+	input   [11:0]  d;
+	output   [11:0]  q;
+
+	wire  [11:0]   wire_dffpipe5_q;
+
+	fifo_4k_dffpipe_em2   dffpipe5
+	( 
+	.clock(clock),
+	.clrn(clrn),
+	.d(d),
+	.q(wire_dffpipe5_q));
+	assign
+		q = wire_dffpipe5_q;
+endmodule //fifo_4k_alt_synch_pipe_em2
+
+
+//lpm_add_sub DEVICE_FAMILY="Cyclone" LPM_DIRECTION="SUB" LPM_WIDTH=12 dataa datab result
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+//synthesis_resources = lut 12 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_add_sub_b18
+	( 
+	dataa,
+	datab,
+	result) /* synthesis synthesis_clearbox=1 */;
+	input   [11:0]  dataa;
+	input   [11:0]  datab;
+	output   [11:0]  result;
+
+	wire  [11:0]   wire_add_sub_cella_combout;
+	wire  [0:0]   wire_add_sub_cella_0cout;
+	wire  [0:0]   wire_add_sub_cella_1cout;
+	wire  [0:0]   wire_add_sub_cella_2cout;
+	wire  [0:0]   wire_add_sub_cella_3cout;
+	wire  [0:0]   wire_add_sub_cella_4cout;
+	wire  [0:0]   wire_add_sub_cella_5cout;
+	wire  [0:0]   wire_add_sub_cella_6cout;
+	wire  [0:0]   wire_add_sub_cella_7cout;
+	wire  [0:0]   wire_add_sub_cella_8cout;
+	wire  [0:0]   wire_add_sub_cella_9cout;
+	wire  [0:0]   wire_add_sub_cella_10cout;
+	wire  [11:0]   wire_add_sub_cella_dataa;
+	wire  [11:0]   wire_add_sub_cella_datab;
+
+	cyclone_lcell   add_sub_cella_0
+	( 
+	.cin(1'b1),
+	.combout(wire_add_sub_cella_combout[0:0]),
+	.cout(wire_add_sub_cella_0cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[0:0]),
+	.datab(wire_add_sub_cella_datab[0:0]),
+	.regout()
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.clk(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.ena(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sclr(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		add_sub_cella_0.cin_used = "true",
+		add_sub_cella_0.lut_mask = "69b2",
+		add_sub_cella_0.operation_mode = "arithmetic",
+		add_sub_cella_0.sum_lutc_input = "cin",
+		add_sub_cella_0.lpm_type = "cyclone_lcell";
+	cyclone_lcell   add_sub_cella_1
+	( 
+	.cin(wire_add_sub_cella_0cout[0:0]),
+	.combout(wire_add_sub_cella_combout[1:1]),
+	.cout(wire_add_sub_cella_1cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[1:1]),
+	.datab(wire_add_sub_cella_datab[1:1]),
+	.regout()
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.clk(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.ena(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sclr(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		add_sub_cella_1.cin_used = "true",
+		add_sub_cella_1.lut_mask = "69b2",
+		add_sub_cella_1.operation_mode = "arithmetic",
+		add_sub_cella_1.sum_lutc_input = "cin",
+		add_sub_cella_1.lpm_type = "cyclone_lcell";
+	cyclone_lcell   add_sub_cella_2
+	( 
+	.cin(wire_add_sub_cella_1cout[0:0]),
+	.combout(wire_add_sub_cella_combout[2:2]),
+	.cout(wire_add_sub_cella_2cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[2:2]),
+	.datab(wire_add_sub_cella_datab[2:2]),
+	.regout()
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.clk(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.ena(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sclr(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		add_sub_cella_2.cin_used = "true",
+		add_sub_cella_2.lut_mask = "69b2",
+		add_sub_cella_2.operation_mode = "arithmetic",
+		add_sub_cella_2.sum_lutc_input = "cin",
+		add_sub_cella_2.lpm_type = "cyclone_lcell";
+	cyclone_lcell   add_sub_cella_3
+	( 
+	.cin(wire_add_sub_cella_2cout[0:0]),
+	.combout(wire_add_sub_cella_combout[3:3]),
+	.cout(wire_add_sub_cella_3cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[3:3]),
+	.datab(wire_add_sub_cella_datab[3:3]),
+	.regout()
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.clk(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.ena(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sclr(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		add_sub_cella_3.cin_used = "true",
+		add_sub_cella_3.lut_mask = "69b2",
+		add_sub_cella_3.operation_mode = "arithmetic",
+		add_sub_cella_3.sum_lutc_input = "cin",
+		add_sub_cella_3.lpm_type = "cyclone_lcell";
+	cyclone_lcell   add_sub_cella_4
+	( 
+	.cin(wire_add_sub_cella_3cout[0:0]),
+	.combout(wire_add_sub_cella_combout[4:4]),
+	.cout(wire_add_sub_cella_4cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[4:4]),
+	.datab(wire_add_sub_cella_datab[4:4]),
+	.regout()
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.clk(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.ena(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sclr(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		add_sub_cella_4.cin_used = "true",
+		add_sub_cella_4.lut_mask = "69b2",
+		add_sub_cella_4.operation_mode = "arithmetic",
+		add_sub_cella_4.sum_lutc_input = "cin",
+		add_sub_cella_4.lpm_type = "cyclone_lcell";
+	cyclone_lcell   add_sub_cella_5
+	( 
+	.cin(wire_add_sub_cella_4cout[0:0]),
+	.combout(wire_add_sub_cella_combout[5:5]),
+	.cout(wire_add_sub_cella_5cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[5:5]),
+	.datab(wire_add_sub_cella_datab[5:5]),
+	.regout()
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.clk(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.ena(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sclr(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		add_sub_cella_5.cin_used = "true",
+		add_sub_cella_5.lut_mask = "69b2",
+		add_sub_cella_5.operation_mode = "arithmetic",
+		add_sub_cella_5.sum_lutc_input = "cin",
+		add_sub_cella_5.lpm_type = "cyclone_lcell";
+	cyclone_lcell   add_sub_cella_6
+	( 
+	.cin(wire_add_sub_cella_5cout[0:0]),
+	.combout(wire_add_sub_cella_combout[6:6]),
+	.cout(wire_add_sub_cella_6cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[6:6]),
+	.datab(wire_add_sub_cella_datab[6:6]),
+	.regout()
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.clk(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.ena(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sclr(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		add_sub_cella_6.cin_used = "true",
+		add_sub_cella_6.lut_mask = "69b2",
+		add_sub_cella_6.operation_mode = "arithmetic",
+		add_sub_cella_6.sum_lutc_input = "cin",
+		add_sub_cella_6.lpm_type = "cyclone_lcell";
+	cyclone_lcell   add_sub_cella_7
+	( 
+	.cin(wire_add_sub_cella_6cout[0:0]),
+	.combout(wire_add_sub_cella_combout[7:7]),
+	.cout(wire_add_sub_cella_7cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[7:7]),
+	.datab(wire_add_sub_cella_datab[7:7]),
+	.regout()
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.clk(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.ena(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sclr(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		add_sub_cella_7.cin_used = "true",
+		add_sub_cella_7.lut_mask = "69b2",
+		add_sub_cella_7.operation_mode = "arithmetic",
+		add_sub_cella_7.sum_lutc_input = "cin",
+		add_sub_cella_7.lpm_type = "cyclone_lcell";
+	cyclone_lcell   add_sub_cella_8
+	( 
+	.cin(wire_add_sub_cella_7cout[0:0]),
+	.combout(wire_add_sub_cella_combout[8:8]),
+	.cout(wire_add_sub_cella_8cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[8:8]),
+	.datab(wire_add_sub_cella_datab[8:8]),
+	.regout()
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.clk(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.ena(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sclr(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		add_sub_cella_8.cin_used = "true",
+		add_sub_cella_8.lut_mask = "69b2",
+		add_sub_cella_8.operation_mode = "arithmetic",
+		add_sub_cella_8.sum_lutc_input = "cin",
+		add_sub_cella_8.lpm_type = "cyclone_lcell";
+	cyclone_lcell   add_sub_cella_9
+	( 
+	.cin(wire_add_sub_cella_8cout[0:0]),
+	.combout(wire_add_sub_cella_combout[9:9]),
+	.cout(wire_add_sub_cella_9cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[9:9]),
+	.datab(wire_add_sub_cella_datab[9:9]),
+	.regout()
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.clk(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.ena(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sclr(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		add_sub_cella_9.cin_used = "true",
+		add_sub_cella_9.lut_mask = "69b2",
+		add_sub_cella_9.operation_mode = "arithmetic",
+		add_sub_cella_9.sum_lutc_input = "cin",
+		add_sub_cella_9.lpm_type = "cyclone_lcell";
+	cyclone_lcell   add_sub_cella_10
+	( 
+	.cin(wire_add_sub_cella_9cout[0:0]),
+	.combout(wire_add_sub_cella_combout[10:10]),
+	.cout(wire_add_sub_cella_10cout[0:0]),
+	.dataa(wire_add_sub_cella_dataa[10:10]),
+	.datab(wire_add_sub_cella_datab[10:10]),
+	.regout()
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.clk(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.ena(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sclr(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		add_sub_cella_10.cin_used = "true",
+		add_sub_cella_10.lut_mask = "69b2",
+		add_sub_cella_10.operation_mode = "arithmetic",
+		add_sub_cella_10.sum_lutc_input = "cin",
+		add_sub_cella_10.lpm_type = "cyclone_lcell";
+	cyclone_lcell   add_sub_cella_11
+	( 
+	.cin(wire_add_sub_cella_10cout[0:0]),
+	.combout(wire_add_sub_cella_combout[11:11]),
+	.cout(),
+	.dataa(wire_add_sub_cella_dataa[11:11]),
+	.datab(wire_add_sub_cella_datab[11:11]),
+	.regout()
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.clk(1'b1),
+	.datac(1'b1),
+	.datad(1'b1),
+	.ena(1'b1),
+	.inverta(1'b0),
+	.regcascin(1'b0),
+	.sclr(1'b0),
+	.sload(1'b0)
+	`ifdef FORMAL_VERIFICATION
+	`else
+	// synopsys translate_on
+	`endif
+	// synopsys translate_off
+	,
+	.cin0(),
+	.cin1(),
+	.cout0(),
+	.cout1(),
+	.devclrn(),
+	.devpor()
+	// synopsys translate_on
+	);
+	defparam
+		add_sub_cella_11.cin_used = "true",
+		add_sub_cella_11.lut_mask = "6969",
+		add_sub_cella_11.operation_mode = "normal",
+		add_sub_cella_11.sum_lutc_input = "cin",
+		add_sub_cella_11.lpm_type = "cyclone_lcell";
+	assign
+		wire_add_sub_cella_dataa = dataa,
+		wire_add_sub_cella_datab = datab;
+	assign
+		result = wire_add_sub_cella_combout;
+endmodule //fifo_4k_add_sub_b18
+
+
+//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+
+//lpm_compare DEVICE_FAMILY="Cyclone" LPM_WIDTH=12 aeb dataa datab
+//VERSION_BEGIN 5.0 cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_stratix 2005:06:02:09:53:04:SJ cbx_stratixii 2004:12:22:13:27:12:SJ  VERSION_END
+
+//synthesis_resources = lut 104 M4K 16 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+module  fifo_4k_dcfifo_6cq
+	( 
+	aclr,
+	data,
+	q,
+	rdclk,
+	rdempty,
+	rdreq,
+	rdusedw,
+	wrclk,
+	wrfull,
+	wrreq,
+	wrusedw) /* synthesis synthesis_clearbox=1 */
+		/* synthesis ALTERA_ATTRIBUTE="AUTO_SHIFT_REGISTER_RECOGNITION=OFF;{ -from \"rdptr_g|power_modified_counter_values\" -to \"ws_dgrp|dffpipe5|dffe6a\" }CUT=ON;{ -from \"delayed_wrptr_g\" -to \"rs_dgwp|dffpipe5|dffe6a\" }CUT=ON" */;
+	input   aclr;
+	input   [15:0]  data;
+	output   [15:0]  q;
+	input   rdclk;
+	output   rdempty;
+	input   rdreq;
+	output   [11:0]  rdusedw;
+	input   wrclk;
+	output   wrfull;
+	input   wrreq;
+	output   [11:0]  wrusedw;
+
+	wire  [11:0]   wire_rdptr_g_gray2bin_bin;
+	wire  [11:0]   wire_rs_dgwp_gray2bin_bin;
+	wire  [11:0]   wire_wrptr_g_gray2bin_bin;
+	wire  [11:0]   wire_ws_dgrp_gray2bin_bin;
+	wire  [11:0]   wire_rdptr_g_q;
+	wire  [11:0]   wire_rdptr_g1p_q;
+	wire  [11:0]   wire_wrptr_g1p_q;
+	wire  [15:0]   wire_fifo_ram_q_b;
+	reg	[11:0]	delayed_wrptr_g;
+	reg	[11:0]	wrptr_g;
+	wire  [11:0]   wire_rs_brp_q;
+	wire  [11:0]   wire_rs_bwp_q;
+	wire  [11:0]   wire_rs_dgwp_q;
+	wire  [11:0]   wire_ws_brp_q;
+	wire  [11:0]   wire_ws_bwp_q;
+	wire  [11:0]   wire_ws_dgrp_q;
+	wire  [11:0]   wire_rdusedw_sub_result;
+	wire  [11:0]   wire_wrusedw_sub_result;
+	reg	wire_rdempty_eq_comp_aeb_int;
+	wire	wire_rdempty_eq_comp_aeb;
+	wire	[11:0]	wire_rdempty_eq_comp_dataa;
+	wire	[11:0]	wire_rdempty_eq_comp_datab;
+	reg	wire_wrfull_eq_comp_aeb_int;
+	wire	wire_wrfull_eq_comp_aeb;
+	wire	[11:0]	wire_wrfull_eq_comp_dataa;
+	wire	[11:0]	wire_wrfull_eq_comp_datab;
+	wire  int_rdempty;
+	wire  int_wrfull;
+	wire  valid_rdreq;
+	wire  valid_wrreq;
+
+	fifo_4k_a_gray2bin_9m4   rdptr_g_gray2bin
+	( 
+	.bin(wire_rdptr_g_gray2bin_bin),
+	.gray(wire_rdptr_g_q));
+	fifo_4k_a_gray2bin_9m4   rs_dgwp_gray2bin
+	( 
+	.bin(wire_rs_dgwp_gray2bin_bin),
+	.gray(wire_rs_dgwp_q));
+	fifo_4k_a_gray2bin_9m4   wrptr_g_gray2bin
+	( 
+	.bin(wire_wrptr_g_gray2bin_bin),
+	.gray(wrptr_g));
+	fifo_4k_a_gray2bin_9m4   ws_dgrp_gray2bin
+	( 
+	.bin(wire_ws_dgrp_gray2bin_bin),
+	.gray(wire_ws_dgrp_q));
+	fifo_4k_a_graycounter_826   rdptr_g
+	( 
+	.aclr(aclr),
+	.clock(rdclk),
+	.cnt_en(valid_rdreq),
+	.q(wire_rdptr_g_q));
+	fifo_4k_a_graycounter_3r6   rdptr_g1p
+	( 
+	.aclr(aclr),
+	.clock(rdclk),
+	.cnt_en(valid_rdreq),
+	.q(wire_rdptr_g1p_q));
+	fifo_4k_a_graycounter_3r6   wrptr_g1p
+	( 
+	.aclr(aclr),
+	.clock(wrclk),
+	.cnt_en(valid_wrreq),
+	.q(wire_wrptr_g1p_q));
+	fifo_4k_altsyncram_8pl   fifo_ram
+	( 
+	.address_a(wrptr_g),
+	.address_b(((wire_rdptr_g_q & {12{int_rdempty}}) | (wire_rdptr_g1p_q & {12{(~ int_rdempty)}}))),
+	.clock0(wrclk),
+	.clock1(rdclk),
+	.clocken1((valid_rdreq | int_rdempty)),
+	.data_a(data),
+	.q_b(wire_fifo_ram_q_b),
+	.wren_a(valid_wrreq));
+	// synopsys translate_off
+	initial
+		delayed_wrptr_g = 0;
+	// synopsys translate_on
+	always @ ( posedge wrclk or  posedge aclr)
+		if (aclr == 1'b1) delayed_wrptr_g <= 12'b0;
+		else  delayed_wrptr_g <= wrptr_g;
+	// synopsys translate_off
+	initial
+		wrptr_g = 0;
+	// synopsys translate_on
+	always @ ( posedge wrclk or  posedge aclr)
+		if (aclr == 1'b1) wrptr_g <= 12'b0;
+		else if  (valid_wrreq == 1'b1)   wrptr_g <= wire_wrptr_g1p_q;
+	fifo_4k_dffpipe_bb3   rs_brp
+	( 
+	.clock(rdclk),
+	.clrn((~ aclr)),
+	.d(wire_rdptr_g_gray2bin_bin),
+	.q(wire_rs_brp_q));
+	fifo_4k_dffpipe_bb3   rs_bwp
+	( 
+	.clock(rdclk),
+	.clrn((~ aclr)),
+	.d(wire_rs_dgwp_gray2bin_bin),
+	.q(wire_rs_bwp_q));
+	fifo_4k_alt_synch_pipe_em2   rs_dgwp
+	( 
+	.clock(rdclk),
+	.clrn((~ aclr)),
+	.d(delayed_wrptr_g),
+	.q(wire_rs_dgwp_q));
+	fifo_4k_dffpipe_bb3   ws_brp
+	( 
+	.clock(wrclk),
+	.clrn((~ aclr)),
+	.d(wire_ws_dgrp_gray2bin_bin),
+	.q(wire_ws_brp_q));
+	fifo_4k_dffpipe_bb3   ws_bwp
+	( 
+	.clock(wrclk),
+	.clrn((~ aclr)),
+	.d(wire_wrptr_g_gray2bin_bin),
+	.q(wire_ws_bwp_q));
+	fifo_4k_alt_synch_pipe_em2   ws_dgrp
+	( 
+	.clock(wrclk),
+	.clrn((~ aclr)),
+	.d(wire_rdptr_g_q),
+	.q(wire_ws_dgrp_q));
+	fifo_4k_add_sub_b18   rdusedw_sub
+	( 
+	.dataa(wire_rs_bwp_q),
+	.datab(wire_rs_brp_q),
+	.result(wire_rdusedw_sub_result));
+	fifo_4k_add_sub_b18   wrusedw_sub
+	( 
+	.dataa(wire_ws_bwp_q),
+	.datab(wire_ws_brp_q),
+	.result(wire_wrusedw_sub_result));
+	always @(wire_rdempty_eq_comp_dataa or wire_rdempty_eq_comp_datab)
+		if (wire_rdempty_eq_comp_dataa == wire_rdempty_eq_comp_datab) 
+			begin
+				wire_rdempty_eq_comp_aeb_int = 1'b1;
+			end
+		else
+			begin
+				wire_rdempty_eq_comp_aeb_int = 1'b0;
+			end
+	assign
+		wire_rdempty_eq_comp_aeb = wire_rdempty_eq_comp_aeb_int;
+	assign
+		wire_rdempty_eq_comp_dataa = wire_rs_dgwp_q,
+		wire_rdempty_eq_comp_datab = wire_rdptr_g_q;
+	always @(wire_wrfull_eq_comp_dataa or wire_wrfull_eq_comp_datab)
+		if (wire_wrfull_eq_comp_dataa == wire_wrfull_eq_comp_datab) 
+			begin
+				wire_wrfull_eq_comp_aeb_int = 1'b1;
+			end
+		else
+			begin
+				wire_wrfull_eq_comp_aeb_int = 1'b0;
+			end
+	assign
+		wire_wrfull_eq_comp_aeb = wire_wrfull_eq_comp_aeb_int;
+	assign
+		wire_wrfull_eq_comp_dataa = wire_ws_dgrp_q,
+		wire_wrfull_eq_comp_datab = wire_wrptr_g1p_q;
+	assign
+		int_rdempty = wire_rdempty_eq_comp_aeb,
+		int_wrfull = wire_wrfull_eq_comp_aeb,
+		q = wire_fifo_ram_q_b,
+		rdempty = int_rdempty,
+		rdusedw = wire_rdusedw_sub_result,
+		valid_rdreq = rdreq,
+		valid_wrreq = wrreq,
+		wrfull = int_wrfull,
+		wrusedw = wire_wrusedw_sub_result;
+endmodule //fifo_4k_dcfifo_6cq
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_4k (
+	data,
+	wrreq,
+	rdreq,
+	rdclk,
+	wrclk,
+	aclr,
+	q,
+	rdempty,
+	rdusedw,
+	wrfull,
+	wrusedw)/* synthesis synthesis_clearbox = 1 */;
+
+	input	[15:0]  data;
+	input	  wrreq;
+	input	  rdreq;
+	input	  rdclk;
+	input	  wrclk;
+	input	  aclr;
+	output	[15:0]  q;
+	output	  rdempty;
+	output	[11:0]  rdusedw;
+	output	  wrfull;
+	output	[11:0]  wrusedw;
+
+	wire  sub_wire0;
+	wire [11:0] sub_wire1;
+	wire  sub_wire2;
+	wire [15:0] sub_wire3;
+	wire [11:0] sub_wire4;
+	wire  rdempty = sub_wire0;
+	wire [11:0] wrusedw = sub_wire1[11:0];
+	wire  wrfull = sub_wire2;
+	wire [15:0] q = sub_wire3[15:0];
+	wire [11:0] rdusedw = sub_wire4[11:0];
+
+	fifo_4k_dcfifo_6cq	fifo_4k_dcfifo_6cq_component (
+				.wrclk (wrclk),
+				.rdreq (rdreq),
+				.aclr (aclr),
+				.rdclk (rdclk),
+				.wrreq (wrreq),
+				.data (data),
+				.rdempty (sub_wire0),
+				.wrusedw (sub_wire1),
+				.wrfull (sub_wire2),
+				.q (sub_wire3),
+				.rdusedw (sub_wire4));
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: Depth NUMERIC "4096"
+// Retrieval info: PRIVATE: Clock NUMERIC "4"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "4096"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "12"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
+// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
+// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
+// Retrieval info: USED_PORT: rdusedw 0 0 12 0 OUTPUT NODEFVAL rdusedw[11..0]
+// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
+// Retrieval info: USED_PORT: wrusedw 0 0 12 0 OUTPUT NODEFVAL wrusedw[11..0]
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
+// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
+// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
+// Retrieval info: CONNECT: rdusedw 0 0 12 0 @rdusedw 0 0 12 0
+// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
+// Retrieval info: CONNECT: wrusedw 0 0 12 0 @wrusedw 0 0 12 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_waveforms.html TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_4k_wave*.jpg FALSE