Merged features/inband-usb r5224:6306 into trunk. This is work-in-progress on inband signaling for the USRP1.

git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6307 221aa14e-8319-0410-a670-987f0aec2ac5

1 files changed, 167 insertions, 0 deletions

diff --git a/megacells/fifo_2kx16.v b/megacells/fifo_2kx16.v
new file mode 100755
index 000000000..eb229769d
--- /dev/null
+++ b/megacells/fifo_2kx16.v
@@ -0,0 +1,167 @@
+// megafunction wizard: %FIFO%

+// GENERATION: STANDARD

+// VERSION: WM1.0

+// MODULE: scfifo 

+

+// ============================================================

+// File Name: fifo_2kx16.v

+// Megafunction Name(s):

+// 			scfifo

+// ============================================================

+// ************************************************************

+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!

+//

+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition

+// ************************************************************

+

+

+//Copyright (C) 1991-2006 Altera Corporation

+//Your use of Altera Corporation's design tools, logic functions 

+//and other software and tools, and its AMPP partner logic 

+//functions, and any output files any of the foregoing 

+//(including device programming or simulation files), and any 

+//associated documentation or information are expressly subject 

+//to the terms and conditions of the Altera Program License 

+//Subscription Agreement, Altera MegaCore Function License 

+//Agreement, or other applicable license agreement, including, 

+//without limitation, that your use is for the sole purpose of 

+//programming logic devices manufactured by Altera and sold by 

+//Altera or its authorized distributors.  Please refer to the 

+//applicable agreement for further details.

+

+

+// synopsys translate_off

+`timescale 1 ps / 1 ps

+// synopsys translate_on

+module fifo_2kx16 (

+	aclr,

+	clock,

+	data,

+	rdreq,

+	wrreq,

+	empty,

+	full,

+	q,

+	usedw);

+

+	input	  aclr;

+	input	  clock;

+	input	[15:0]  data;

+	input	  rdreq;

+	input	  wrreq;

+	output	  empty;

+	output	  full;

+	output	[15:0]  q;

+	output	[10:0]  usedw;

+

+	wire [10:0] sub_wire0;

+	wire  sub_wire1;

+	wire [15:0] sub_wire2;

+	wire  sub_wire3;

+	wire [10:0] usedw = sub_wire0[10:0];

+	wire  empty = sub_wire1;

+	wire [15:0] q = sub_wire2[15:0];

+	wire  full = sub_wire3;

+

+	scfifo	scfifo_component (

+				.rdreq (rdreq),

+				.aclr (aclr),

+				.clock (clock),

+				.wrreq (wrreq),

+				.data (data),

+				.usedw (sub_wire0),

+				.empty (sub_wire1),

+				.q (sub_wire2),

+				.full (sub_wire3)

+				// synopsys translate_off

+				,

+				.almost_empty (),

+				.sclr (),

+				.almost_full ()

+				// synopsys translate_on

+				);

+	defparam

+		scfifo_component.add_ram_output_register = "OFF",

+		scfifo_component.intended_device_family = "Cyclone",

+		scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",

+		scfifo_component.lpm_numwords = 2048,

+		scfifo_component.lpm_showahead = "OFF",

+		scfifo_component.lpm_type = "scfifo",

+		scfifo_component.lpm_width = 16,

+		scfifo_component.lpm_widthu = 11,

+		scfifo_component.overflow_checking = "ON",

+		scfifo_component.underflow_checking = "ON",

+		scfifo_component.use_eab = "ON";

+

+

+endmodule

+

+// ============================================================

+// CNX file retrieval info

+// ============================================================

+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"

+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"

+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"

+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"

+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"

+// Retrieval info: PRIVATE: Clock NUMERIC "0"

+// Retrieval info: PRIVATE: Depth NUMERIC "2048"

+// Retrieval info: PRIVATE: Empty NUMERIC "1"

+// Retrieval info: PRIVATE: Full NUMERIC "1"

+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"

+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"

+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"

+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"

+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"

+// Retrieval info: PRIVATE: Optimize NUMERIC "2"

+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"

+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"

+// Retrieval info: PRIVATE: UsedW NUMERIC "1"

+// Retrieval info: PRIVATE: Width NUMERIC "16"

+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"

+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"

+// Retrieval info: PRIVATE: rsFull NUMERIC "0"

+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"

+// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"

+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"

+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"

+// Retrieval info: PRIVATE: wsFull NUMERIC "1"

+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"

+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"

+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"

+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"

+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "2048"

+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"

+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"

+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"

+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "11"

+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"

+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"

+// Retrieval info: CONSTANT: USE_EAB STRING "ON"

+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr

+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock

+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]

+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty

+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full

+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]

+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq

+// Retrieval info: USED_PORT: usedw 0 0 11 0 OUTPUT NODEFVAL usedw[10..0]

+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq

+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0

+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0

+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0

+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0

+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0

+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0

+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0

+// Retrieval info: CONNECT: usedw 0 0 11 0 @usedw 0 0 11 0

+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0

+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.v TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.inc TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.cmp TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16.bsf TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_inst.v TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_bb.v TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_waveforms.html TRUE

+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2kx16_wave*.jpg FALSE