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author | eb <eb@221aa14e-8319-0410-a670-987f0aec2ac5> | 2007-09-05 01:43:43 +0000 |
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committer | eb <eb@221aa14e-8319-0410-a670-987f0aec2ac5> | 2007-09-05 01:43:43 +0000 |
commit | 3872941ae16eab596f48429057b3490b256bce6d (patch) | |
tree | 0f5eddd6f0c7299878dca972412a1d3be76e91e5 /megacells/fifo_2kx16.cmp | |
parent | 632d8e2dd3c961326f985add8d5d97db5ffcf314 (diff) | |
download | uhd-3872941ae16eab596f48429057b3490b256bce6d.tar.gz uhd-3872941ae16eab596f48429057b3490b256bce6d.tar.bz2 uhd-3872941ae16eab596f48429057b3490b256bce6d.zip |
Merged features/inband-usb r5224:6306 into trunk. This is work-in-progress on inband signaling for the USRP1.
git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@6307 221aa14e-8319-0410-a670-987f0aec2ac5
Diffstat (limited to 'megacells/fifo_2kx16.cmp')
-rwxr-xr-x | megacells/fifo_2kx16.cmp | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/megacells/fifo_2kx16.cmp b/megacells/fifo_2kx16.cmp new file mode 100755 index 000000000..96c34d8d7 --- /dev/null +++ b/megacells/fifo_2kx16.cmp @@ -0,0 +1,29 @@ +--Copyright (C) 1991-2006 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions
+--and other software and tools, and its AMPP partner logic
+--functions, and any output files any of the foregoing
+--(including device programming or simulation files), and any
+--associated documentation or information are expressly subject
+--to the terms and conditions of the Altera Program License
+--Subscription Agreement, Altera MegaCore Function License
+--Agreement, or other applicable license agreement, including,
+--without limitation, that your use is for the sole purpose of
+--programming logic devices manufactured by Altera and sold by
+--Altera or its authorized distributors. Please refer to the
+--applicable agreement for further details.
+
+
+component fifo_2kx16
+ PORT
+ (
+ aclr : IN STD_LOGIC ;
+ clock : IN STD_LOGIC ;
+ data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
+ rdreq : IN STD_LOGIC ;
+ wrreq : IN STD_LOGIC ;
+ empty : OUT STD_LOGIC ;
+ full : OUT STD_LOGIC ;
+ q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
+ usedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
+ );
+end component;
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