diff options
| author | Martin Braun <martin.braun@ettus.com> | 2016-11-14 14:30:34 -0800 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2018-07-25 15:34:03 -0700 |
| commit | 988515ab19a715773086a7a8c023ddb8249c7e37 (patch) | |
| tree | 71c861c3a1d0a5e295dad5939358dd30e0a33f3b /images | |
| parent | 8b16ab706fb4768f802ddb65a81fc26e1562cb0d (diff) | |
| download | uhd-988515ab19a715773086a7a8c023ddb8249c7e37.tar.gz uhd-988515ab19a715773086a7a8c023ddb8249c7e37.tar.bz2 uhd-988515ab19a715773086a7a8c023ddb8249c7e37.zip | |
Device3: Change packet-based flow control to byte-based flow control
Diffstat (limited to 'images')
| -rw-r--r-- | images/manifest.txt | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/images/manifest.txt b/images/manifest.txt index 266f564ab..4978e75b6 100644 --- a/images/manifest.txt +++ b/images/manifest.txt @@ -1,18 +1,18 @@ # UHD Image Manifest File # Target hash url SHA256 # X300-Series -x3xx_x310_fpga_default fpga-f279264 x3xx/fpga-f279264/x3xx_x310_fpga_default-gf279264.zip a9d0f4b9f75bca4724333f3320989b2f9a56cf75e3a7bc569b4e868af3feb095 -x3xx_x300_fpga_default fpga-f279264 x3xx/fpga-f279264/x3xx_x300_fpga_default-gf279264.zip 872c3833dc03ed8ff5a6dea2053d7ccb353a63ba760b82c4a48c3c3b839a725c +x3xx_x310_fpga_default fpga-c398755 x3xx/fpga-c398755/x3xx_x310_fpga_default-gc398755.zip 22bf9147373bae395063ed0f2c016f2d1c47da01a40e042fc7f84e9e2eecd331 +x3xx_x300_fpga_default fpga-c398755 x3xx/fpga-c398755/x3xx_x300_fpga_default-gc398755.zip 19c5ff0109cc3c09a698bf2349a7b1f0573528a8b8d29f6e37720ec7c263efe6 # Example daughterboard targets (none currently exist) #x3xx_twinrx_cpld_default example_target #dboard_ubx_cpld_default example_target # E-Series -e3xx_e310_fpga_default fpga-f279264 e3xx/fpga-f279264/e3xx_e310_fpga_default-gf279264.zip 707428e8703b29ad9df60725f25fed78223deab5f4a7becf4ed1886b43f18f92 +e3xx_e310_fpga_default fpga-c398755 e3xx/fpga-c398755/e3xx_e310_fpga_default-gc398755.zip 707428e8703b29ad9df60725f25fed78223deab5f4a7becf4ed1886b43f18f92 e3xx_e310_fpga_rfnoc fpga-d6a878b e3xx/fpga-d6a878b/e3xx_e310_fpga_rfnoc-gd6a878b.zip 5c9b89fb6293423644868c22e914de386a9af39ff031da6800a1cf39a90ea73b # N300-Series -n3xx_n310_fpga_default fpga-f279264 n3xx/fpga-f279264/n3xx_n310_fpga_default-gf279264.zip e31c2a71014e7fdb140e00ef3f6e9814b720e0f8de4544d2bad8a50cf1c61ce1 -n3xx_n300_fpga_default fpga-f279264 n3xx/fpga-f279264/n3xx_n300_fpga_default-gf279264.zip 83f880d2b79f666a8fe660aa949cd1c1eaf5256d31036696fd270ae59491acc6 +n3xx_n310_fpga_default fpga-c398755 n3xx/fpga-c398755/n3xx_n310_fpga_default-gc398755.zip 6637bf9ce4a9c212bd30494aa5e0117e4a076a367a5370b4542053beed69e85a +n3xx_n300_fpga_default fpga-c398755 n3xx/fpga-c398755/n3xx_n300_fpga_default-gc398755.zip 2d45af7c433449a3b0f4aca90bf30b3c1bc918b452893d22c8397f086e2812d4 #n3xx_n310_fpga_aurora fpga-1107862 n3xx/fpga-1107862/n3xx_n310_fpga_aurora-g1107862.zip 3926d6b247a8f931809460d3957cec51f8407cd3f7aea6f4f3b91d1bbb427c7d #n3xx_n300_fpga_aurora fpga-1107862 n3xx/fpga-1107862/n3xx_n300_fpga_aurora-g1107862.zip e34e9343572adfba905433a1570cb394fe45207d442268d0fa400c3406253530 #n3xx_n310_cpld_default fpga-6bea23d n3xx/fpga-6bea23d/n3xx_n310_cpld_default-g6bea23d.zip 0 |