diff options
| author | Ashish Chaudhari <ashish@ettus.com> | 2018-07-19 17:08:45 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2018-07-24 14:39:08 -0700 |
| commit | 8b16ab706fb4768f802ddb65a81fc26e1562cb0d (patch) | |
| tree | 884a58e82ede9298795308688e898a01c931ac1f /images | |
| parent | dd9cc213ca5bd49783b3942d8486278aed8735c8 (diff) | |
| download | uhd-8b16ab706fb4768f802ddb65a81fc26e1562cb0d.tar.gz uhd-8b16ab706fb4768f802ddb65a81fc26e1562cb0d.tar.bz2 uhd-8b16ab706fb4768f802ddb65a81fc26e1562cb0d.zip | |
rfnoc: Enabled SW flush mechanism impl'd in noc_shell
- UHD will now "disconnect" the noc_block data-path from
the crossbar when the block's dtor is invoked. This allows
long running or slow blocks to empty out rapidly during
teardown.
- UHD will also attempt to flush at init time in case a block
is destroyed abnormally. The goal of the flush mechanism is
to not lock up the FPGA
- noc_shell compat number is now 3
Diffstat (limited to 'images')
| -rw-r--r-- | images/manifest.txt | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/images/manifest.txt b/images/manifest.txt index 3fcf88342..266f564ab 100644 --- a/images/manifest.txt +++ b/images/manifest.txt @@ -1,18 +1,18 @@ # UHD Image Manifest File # Target hash url SHA256 # X300-Series -x3xx_x310_fpga_default fpga-1107862 x3xx/fpga-1107862/x3xx_x310_fpga_default-g1107862.zip e1f59031b7c7f5fa166a46636c7b12df6ede5470138cfb71e3860e2945f180e8 -x3xx_x300_fpga_default fpga-1107862 x3xx/fpga-1107862/x3xx_x300_fpga_default-g1107862.zip f90a760837bea61d144cf9940ac24db72959ad075444de0d94c2724a78beb402 +x3xx_x310_fpga_default fpga-f279264 x3xx/fpga-f279264/x3xx_x310_fpga_default-gf279264.zip a9d0f4b9f75bca4724333f3320989b2f9a56cf75e3a7bc569b4e868af3feb095 +x3xx_x300_fpga_default fpga-f279264 x3xx/fpga-f279264/x3xx_x300_fpga_default-gf279264.zip 872c3833dc03ed8ff5a6dea2053d7ccb353a63ba760b82c4a48c3c3b839a725c # Example daughterboard targets (none currently exist) #x3xx_twinrx_cpld_default example_target #dboard_ubx_cpld_default example_target # E-Series -e3xx_e310_fpga_default fpga-1107862 e3xx/fpga-1107862/e3xx_e310_fpga_default-g1107862.zip 52f8451fd459b2a3113903284adea11474a9efb8eaef45b986233c0693f10549 +e3xx_e310_fpga_default fpga-f279264 e3xx/fpga-f279264/e3xx_e310_fpga_default-gf279264.zip 707428e8703b29ad9df60725f25fed78223deab5f4a7becf4ed1886b43f18f92 e3xx_e310_fpga_rfnoc fpga-d6a878b e3xx/fpga-d6a878b/e3xx_e310_fpga_rfnoc-gd6a878b.zip 5c9b89fb6293423644868c22e914de386a9af39ff031da6800a1cf39a90ea73b # N300-Series -n3xx_n310_fpga_default fpga-1107862 n3xx/fpga-1107862/n3xx_n310_fpga_default-g1107862.zip fc80462f2e144d9745b0b480aa513f426e48df46ad18dc85cbb8fdb3cb162355 -n3xx_n300_fpga_default fpga-1107862 n3xx/fpga-1107862/n3xx_n300_fpga_default-g1107862.zip 1e7ae1429825811531149f87f82dfcbc06cf63e1fc3752517edf104950406c36 +n3xx_n310_fpga_default fpga-f279264 n3xx/fpga-f279264/n3xx_n310_fpga_default-gf279264.zip e31c2a71014e7fdb140e00ef3f6e9814b720e0f8de4544d2bad8a50cf1c61ce1 +n3xx_n300_fpga_default fpga-f279264 n3xx/fpga-f279264/n3xx_n300_fpga_default-gf279264.zip 83f880d2b79f666a8fe660aa949cd1c1eaf5256d31036696fd270ae59491acc6 #n3xx_n310_fpga_aurora fpga-1107862 n3xx/fpga-1107862/n3xx_n310_fpga_aurora-g1107862.zip 3926d6b247a8f931809460d3957cec51f8407cd3f7aea6f4f3b91d1bbb427c7d #n3xx_n300_fpga_aurora fpga-1107862 n3xx/fpga-1107862/n3xx_n300_fpga_aurora-g1107862.zip e34e9343572adfba905433a1570cb394fe45207d442268d0fa400c3406253530 #n3xx_n310_cpld_default fpga-6bea23d n3xx/fpga-6bea23d/n3xx_n310_cpld_default-g6bea23d.zip 0 |