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authorSugandha Gupta <sugandha.gupta@ettus.com>2018-07-27 09:29:49 -0700
committerBrent Stapleton <bstapleton@g.hmc.edu>2018-07-31 14:02:02 -0700
commit160025b1f3761aced6f60923f05e8ccf642ffa43 (patch)
tree7a7d5b436e8acc6746bc278a56bdabeb58fa1cc4 /images
parent4f51e3307f45e9fe9d86527b0b58ce784e82b716 (diff)
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e320: Add e320 to images package script
Diffstat (limited to 'images')
-rw-r--r--images/image_package_mapping.py19
1 files changed, 19 insertions, 0 deletions
diff --git a/images/image_package_mapping.py b/images/image_package_mapping.py
index cf5059969..01bd699f3 100644
--- a/images/image_package_mapping.py
+++ b/images/image_package_mapping.py
@@ -24,6 +24,25 @@ PACKAGE_MAPPING = {
"usrp_e3xx_fpga_idle.rpt",
"usrp_e3xx_fpga_idle_sg3.rpt"]
},
+ "e320": {
+ "type": "e3xx",
+ "package_name": "e3xx_e320_fpga_default-g{}.zip",
+ "files": ['usrp_e320_fpga_1G.bit',
+ 'usrp_e320_fpga_1G.bit.md5',
+ 'usrp_e320_fpga_1G.dts',
+ 'usrp_e320_fpga_1G.dts.md5',
+ 'usrp_e320_fpga_1G.rpt',
+ 'usrp_e320_fpga_XG.bit',
+ 'usrp_e320_fpga_XG.bit.md5',
+ 'usrp_e320_fpga_XG.dts',
+ 'usrp_e320_fpga_XG.dts.md5',
+ 'usrp_e320_fpga_XG.rpt',
+ 'usrp_e320_fpga_AA.bit',
+ 'usrp_e320_fpga_AA.bit.md5',
+ 'usrp_e320_fpga_AA.dts',
+ 'usrp_e320_fpga_AA.dts.md5',
+ 'usrp_e320_fpga_AA.rpt']
+ },
"x300": {
"type": "x3xx",
"package_name": "x3xx_x300_fpga_default-g{}.zip",