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| author | michael-west <michael.west@ettus.com> | 2015-04-17 17:43:07 -0700 |
|---|---|---|
| committer | michael-west <michael.west@ettus.com> | 2015-04-17 17:43:07 -0700 |
| commit | 0a103ba2bad243652e8c57732190a18a2ee31d38 (patch) | |
| tree | 98db4fbf7ae0c887341a348164fe326bda37d6fc /images | |
| parent | 24c370781e7ea2e627ce36d3b102a686eaedcf1b (diff) | |
| download | uhd-0a103ba2bad243652e8c57732190a18a2ee31d38.tar.gz uhd-0a103ba2bad243652e8c57732190a18a2ee31d38.tar.bz2 uhd-0a103ba2bad243652e8c57732190a18a2ee31d38.zip | |
B200: Bumped FPGA compat number to 5
B200: Added bit to SR_MISC_OUT register to control ATR mapping from radio to frontend
Diffstat (limited to 'images')
0 files changed, 0 insertions, 0 deletions