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authorMartin Braun <martin.braun@ettus.com>2017-03-15 13:57:57 -0700
committerBrent Stapleton <bstapleton@g.hmc.edu>2018-09-25 16:27:49 -0700
commitb993f4f0d85eee53c1256e0381c3a173af7d5833 (patch)
tree01130b79053f9b297fbc072d81852a9bba2021d4 /images/manifest.txt
parentb9514a6db3ebd06b8ddeddc1283c530d59d60aaf (diff)
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cores: Update rx_frontend_gen3.v controls for 1/4-rate mixer
This tracks the changes on rx_frontend_gen3.v, which was updated to use a quarter-rate downconverter instead of a generic CORDIC. The X3x0 FPGA compat number is incremented as the rx_frontend is part of the device architecture rather than an RFNoC block.
Diffstat (limited to 'images/manifest.txt')
-rw-r--r--images/manifest.txt4
1 files changed, 2 insertions, 2 deletions
diff --git a/images/manifest.txt b/images/manifest.txt
index d292a19a0..52ae6ff80 100644
--- a/images/manifest.txt
+++ b/images/manifest.txt
@@ -1,8 +1,8 @@
# UHD Image Manifest File
# Target hash url SHA256
# X300-Series
-x3xx_x310_fpga_default fpga-615d9b8 x3xx/fpga-615d9b8/x3xx_x310_fpga_default-g615d9b8.zip 9e6f50bb71ee0e6a00159023820504ba1245dbfbd2ba94081cf340aa55015193
-x3xx_x300_fpga_default fpga-615d9b8 x3xx/fpga-615d9b8/x3xx_x300_fpga_default-g615d9b8.zip 0017564dcfaf1c07f86228bd521cd0dd168a7ae6530616466cfcb12155fb361e
+x3xx_x310_fpga_default fpga-340bb076 x3xx/fpga-340bb076/x3xx_x310_fpga_default-g340bb076.zip 2dde0922921e22575210eea9f0afa20df31176059240f9df607c53f7a03a203b
+x3xx_x300_fpga_default fpga-340bb076 x3xx/fpga-340bb076/x3xx_x300_fpga_default-g340bb076.zip bfd78d791067cf072298395667ff5e9779707ed95dce0c2c03c4edc3724ebe25
# Example daughterboard targets (none currently exist)
#x3xx_twinrx_cpld_default example_target
#dboard_ubx_cpld_default example_target