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authorBen Hilburn <ben@ettus.com>2011-10-12 12:32:24 -0700
committerBen Hilburn <ben@ettus.com>2011-10-12 12:32:24 -0700
commit1f6f07b3d42dc763ff1a9ba75fb15463bb338ae0 (patch)
treee4958f6297f8de00881226ce11c7b15571716cea /host
parentac5d3a02a095d1ba8d3089d2d4b5d05b32346cc8 (diff)
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Default adf4350 PLL to fast-lock mode.
Diffstat (limited to 'host')
-rwxr-xr-xhost/lib/ic_reg_maps/gen_adf4350_regs.py2
1 files changed, 1 insertions, 1 deletions
diff --git a/host/lib/ic_reg_maps/gen_adf4350_regs.py b/host/lib/ic_reg_maps/gen_adf4350_regs.py
index e97772843..bccdb2edf 100755
--- a/host/lib/ic_reg_maps/gen_adf4350_regs.py
+++ b/host/lib/ic_reg_maps/gen_adf4350_regs.py
@@ -55,7 +55,7 @@ low_noise_and_spur 2[29:30] 3 low_noise, reserved0, reserved1, low
## address 3
########################################################################
clock_divider_12_bit 3[3:14] 0
-clock_div_mode 3[15:16] 0 clock_divider_off, fast_lock, resync_enable, reserved
+clock_div_mode 3[15:16] 1 clock_divider_off, fast_lock, resync_enable, reserved
##reserved 3[17] 0
cycle_slip_reduction 3[18] 0 disabled, enabled
##reserved 3[19:20] 0