Merge branch 'use_vita_length' into next

2 files changed, 1 insertions, 7 deletions

diff --git a/host/lib/transport/gen_vrt_if_packet.py b/host/lib/transport/gen_vrt_if_packet.py
index 8481932ed..7df2092d8 100755
--- a/host/lib/transport/gen_vrt_if_packet.py
+++ b/host/lib/transport/gen_vrt_if_packet.py
@@ -152,17 +152,11 @@ void vrt::if_hdr_unpack_$(suffix)(
 ){
     //extract vrt header
     boost::uint32_t vrt_hdr_word = $(XE_MACRO)(packet_buff[0]);
-    /*
     size_t packet_words32 = vrt_hdr_word & 0xffff;
 
     //failure case
     if (if_packet_info.num_packet_words32 < packet_words32)
         throw uhd::value_error("bad vrt header or packet fragment");
-    */
-    //Fix for short packets sent from the fpga:
-    //  Use the num_packet_words32 passed in as input,
-    //  and do not use the header bits which could be wrong.
-    size_t packet_words32 = if_packet_info.num_packet_words32;
 
     //extract fields from the header
     if_packet_info.packet_type = if_packet_info_t::packet_type_t(vrt_hdr_word >> 29);
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp
index ab3379dd5..318a75191 100644
--- a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp
+++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp
@@ -33,7 +33,7 @@
 
 uhd::transport::zero_copy_if::sptr usrp_e100_make_mmap_zero_copy(usrp_e100_iface::sptr iface);
 
-static const boost::uint16_t USRP_E_FPGA_COMPAT_NUM = 0x03;
+static const boost::uint16_t USRP_E_FPGA_COMPAT_NUM = 0x04;
 
 //! load an fpga image from a bin file into the usrp-e fpga
 extern void usrp_e100_load_fpga(const std::string &bin_file);