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author | Brent Stapleton <brent.stapleton@ettus.com> | 2017-10-30 17:04:26 -0700 |
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committer | Martin Braun <martin.braun@ettus.com> | 2017-12-22 15:05:05 -0800 |
commit | b4ba46cbf2eddc3c79bd10ea2e4cf9ebc8c6914b (patch) | |
tree | aa8c7a1468d217cf628433e97acffa2a31ce98be /host | |
parent | e63a3e8b740e537750e25bc09a82b8b7b557d4d1 (diff) | |
download | uhd-b4ba46cbf2eddc3c79bd10ea2e4cf9ebc8c6914b.tar.gz uhd-b4ba46cbf2eddc3c79bd10ea2e4cf9ebc8c6914b.tar.bz2 uhd-b4ba46cbf2eddc3c79bd10ea2e4cf9ebc8c6914b.zip |
fpga load: add N310 update FPGA function
-update_fpga loads the FPGA image from the base class's update_component function
-checks if FPGA image is a bit or bin file, and converts to Zynq-compatible binfile if necessary
Diffstat (limited to 'host')
0 files changed, 0 insertions, 0 deletions