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| author | mattprost <matt.prost@ni.com> | 2019-11-18 17:03:20 -0600 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2019-11-25 13:38:34 -0800 |
| commit | 9c0dc99e9db1f80842c6aff4e918475c18c60b6c (patch) | |
| tree | 8e0f320436c3c743c2f446d8823bf6bea9699ed2 /host | |
| parent | d3e1d6e9be75ba8dcd21c2ed466b9e6a316625b0 (diff) | |
| download | uhd-9c0dc99e9db1f80842c6aff4e918475c18c60b6c.tar.gz uhd-9c0dc99e9db1f80842c6aff4e918475c18c60b6c.tar.bz2 uhd-9c0dc99e9db1f80842c6aff4e918475c18c60b6c.zip | |
tools: update FPGA functional verification tests for X3x0 mcr's & dpdk
-Added test cases for the 184.32MHz clock rate.
-Removed some extra test cases for 200MHz clock rate in order to
cut down on test time.
-Added DPDK test cases (copied from 10gige and 2x_10gige test cases).
Diffstat (limited to 'host')
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