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authorJesse Zhang <65556515+jessezhang-ni@users.noreply.github.com>2020-07-24 00:08:18 -0500
committerAaron Rossetto <aaron.rossetto@ni.com>2020-07-30 12:50:30 -0500
commit8db024d43bbb7cd05f5b18dd3d7cec09cac6ec4b (patch)
treeeddf1deb08c700e58996b6ea84fd77948caf0d8c /host
parent25a0e462ddc8ca737415dbae4feb90787e6a35b2 (diff)
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fpga: Add Switchboard RFNoC block
Diffstat (limited to 'host')
-rw-r--r--host/include/uhd/rfnoc/blocks/switchboard.yml41
1 files changed, 41 insertions, 0 deletions
diff --git a/host/include/uhd/rfnoc/blocks/switchboard.yml b/host/include/uhd/rfnoc/blocks/switchboard.yml
new file mode 100644
index 000000000..d2e5665fa
--- /dev/null
+++ b/host/include/uhd/rfnoc/blocks/switchboard.yml
@@ -0,0 +1,41 @@
+schema: rfnoc_modtool_args
+module_name: switchboard
+version: 1.0
+rfnoc_version: 1.0
+chdr_width: 64
+noc_id: 0xBE110000
+
+parameters:
+ NUM_INPUTS: 1
+ NUM_OUTPUTS: 1
+
+clocks:
+ - name: rfnoc_chdr
+ freq: "[]"
+ - name: rfnoc_ctrl
+ freq: "[]"
+
+control:
+ sw_iface: nocscript
+ fpga_iface: ctrlport
+ interface_direction: slave
+ fifo_depth: 32
+ clk_domain: rfnoc_chdr
+ ctrlport:
+ byte_mode: False
+ timed: False
+ has_status: False
+
+data:
+ fpga_iface: axis_chdr
+ clk_domain: rfnoc_chdr
+ inputs:
+ in:
+ num_ports: NUM_INPUTS
+ outputs:
+ out:
+ num_ports: NUM_OUTPUTS
+
+registers:
+
+properties: