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| author | Wade Fife <wade.fife@ettus.com> | 2020-04-06 17:55:15 -0500 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-04-08 17:24:15 -0500 |
| commit | 55e422535292c29de00b80f15b0a49ca3fb94f26 (patch) | |
| tree | 0ecb8f2bebc3fa4295129ea6cd4a29445e6b0537 /host | |
| parent | 3f6a98980557554f1f112d2df6e15415137fd731 (diff) | |
| download | uhd-55e422535292c29de00b80f15b0a49ca3fb94f26.tar.gz uhd-55e422535292c29de00b80f15b0a49ca3fb94f26.tar.bz2 uhd-55e422535292c29de00b80f15b0a49ca3fb94f26.zip | |
fpga: e31x: Update constraints to avoid timing issues
Xilinx changed the way [all_registers -edge_triggered] is treated such
that set_max_delay constraints that use it can cause segmentation and
cause clocks to not be propagated to all endpoints. Changing to
[all_ffs] avoids this potential issue.
Diffstat (limited to 'host')
0 files changed, 0 insertions, 0 deletions