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| author | Wade Fife <wade.fife@ettus.com> | 2020-06-19 15:40:12 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-07-30 12:51:41 -0500 |
| commit | 1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4 (patch) | |
| tree | 12ba30a59c8057e355971797d5cc7bf6910f520b /host | |
| parent | b0b3849a18e1f2d3cb255a507b01ac5e7a9416a0 (diff) | |
| download | uhd-1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4.tar.gz uhd-1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4.tar.bz2 uhd-1e94f85b8bafc3f9acab7ef35d2675fa7e61f6f4.zip | |
fpga: rfnoc: Add Signal Generator RFNoC block
Diffstat (limited to 'host')
| -rw-r--r-- | host/include/uhd/rfnoc/blocks/siggen.yml | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/host/include/uhd/rfnoc/blocks/siggen.yml b/host/include/uhd/rfnoc/blocks/siggen.yml new file mode 100644 index 000000000..78a778479 --- /dev/null +++ b/host/include/uhd/rfnoc/blocks/siggen.yml @@ -0,0 +1,55 @@ +schema: rfnoc_modtool_args +module_name: siggen +version: 1.0 +rfnoc_version: 1.0 +chdr_width: 64 +noc_id: 0x51663110 +makefile_srcs: "${fpga_lib_dir}/blocks/rfnoc_block_siggen/Makefile.srcs" + +parameters: + NUM_PORTS: 1 + +clocks: + - name: rfnoc_chdr + freq: "[]" + - name: rfnoc_ctrl + freq: "[]" + - name: ce + freq: "[]" + +control: + sw_iface: nocscript + fpga_iface: ctrlport + interface_direction: slave + fifo_depth: 32 + clk_domain: ce + ctrlport: + byte_mode: False + timed: False + has_status: False + +data: + fpga_iface: axis_data + clk_domain: ce + inputs: + unused: + item_width: 32 + nipc: 1 + info_fifo_depth: 1 + payload_fifo_depth: 1 + format: sc16 + mdata_sig: ~ + outputs: + out: + num_ports: NUM_PORTS + item_width: 32 + nipc: 1 + info_fifo_depth: 32 + payload_fifo_depth: 32 + sideband_at_end: 0 + format: sc16 + mdata_sig: ~ + +registers: + +properties: |