e320: Add R&D testing procedure

1 files changed, 120 insertions, 12 deletions

diff --git a/host/docs/rd_testing.dox b/host/docs/rd_testing.dox
index 0f54af675..f0c71bb3b 100644
--- a/host/docs/rd_testing.dox
+++ b/host/docs/rd_testing.dox
@@ -77,6 +77,8 @@ tbd
 | DEVTEST-B210-v1     | USRP B210     | None        | \ref rdtesting_devtest_manual | \ref rdtesting_devtest_auto |
 | DEVTEST-B200m-v1    | USRP B200mini | None        | \ref rdtesting_devtest_manual | \ref rdtesting_devtest_auto |
 | DEVTEST-B205m-v1    | USRP B205mini | None        | \ref rdtesting_devtest_manual | \ref rdtesting_devtest_auto |
+| DEVTEST-N310-v1     | USRP N310     | None        | \ref rdtesting_devtest_manual | \ref rdtesting_devtest_auto |
+| DEVTEST-E320-v1     | USRP E320     | None        | \ref rdtesting_devtest_manual | \ref rdtesting_devtest_auto |
 
 The devtests are hardware tests built in to the UHD make system. They can be run
 directly from the build directory and require no configuration.
@@ -143,6 +145,16 @@ respectively.
 
 4. Devtest must report no failures for a 'pass' validation.
 
+### E320 procedure
+
+1. Make sure no peripherals are connected to the device (no
+   GSPDO, front panel GPIO is unconnected).
+2. Run tests for both 1G and XG image.
+3. When the device is connected, simply run `make test_e320` from the command
+   line in the build directory.
+4. Devtest must report no failures for a 'pass' validation.
+
+
 \subsection rdtesting_devtest_auto Devtest: Automatic Test Procedure
 
 As all these tests can be run unsupervised, they can be run automatically given
@@ -229,12 +241,14 @@ debugging: https://kb.ettus.com/Debugging_FPGA_images
 | FPGADSPVERIF-X300-XG-v1  | USRP X300     | 2x UBX      | \ref rdtesting_fpgadspverif_manual | \ref rdtesting_fpgadspverif_auto |
 | FPGADSPVERIF-E310-SG1-v1 | USRP E310 SG1 | None        | \ref rdtesting_fpgadspverif_manual | \ref rdtesting_fpgadspverif_auto |
 | FPGADSPVERIF-E310-SG3-v1 | USRP E310 SG3 | None        | \ref rdtesting_fpgadspverif_manual | \ref rdtesting_fpgadspverif_auto |
+| FPGADSPVERIF-E320-v1     | USRP E320     | None        | \ref rdtesting_fpgadspverif_manual | \ref rdtesting_fpgadspverif_auto |
 
 \subsection rdtesting_fpgadspverif_requirements Requirements
 
 - Signal generator and spectrum analyzer
 - X300 & X310 with 2x UBX daughterboard
 - E310 SG1 & SG3 with SSH access
+- E320 with SSH access
 
 \subsection rdtesting_fpgadspverif_manual FPGA DSP Verification: Manual Test Procedure
 
@@ -248,7 +262,8 @@ to change sample rate while streaming.
    -40 dBm
 3. Inspect the received spectrum using `uhd_fft`
   - X3x0: `uhd_fft -f 915e6 -s 10e6 -g 10`
-  - E3xx: `uhd_fft -f 915e6 -s 2e6 -g 50`
+  - E31x: `uhd_fft -f 915e6 -s 2e6 -g 50`
+  - E320: `uhd_fft -f 915e6 -s 15.36e6 -g 50`
   - Embedded devices will require either using network mode or using X
     forwarding over ssh to run the app natively
 4. In the GUI, inspect the spectrum. There should be a strong tone at the test
@@ -282,7 +297,8 @@ to change sample rate while streaming.
 1. Run calibration on device, if applicable
 2. Using `uhd_siggen_gui`, generate a sine tone TX channel 0 at 915.5 MHz:
   - X3x0: `uhd_siggen_gui -f 915e6 -s 10e6 -g 10 -x 500e3 --sine`
-  - E3xx: `uhd_siggen_gui -f 915e6 -s 2e6 -g 50 -x 500e3 --sine`
+  - E31x: `uhd_siggen_gui -f 915e6 -s 2e6 -g 50 -x 500e3 --sine`
+  - E320: `uhd_siggen_gui -f 915e6 -s 15.36e6 -g 50 -x 500e3 --sine`
 3. Using a spectrum analyzer, inspect the output spectrum. There should be a
    strong tone at the test tone frequency. There may be a small tone at the
    carrier frequency due to DC offset and a quadrature image due to IQ
@@ -295,7 +311,7 @@ to change sample rate while streaming.
 5. Set output tone offset back to 500e3. Change sampling rate as outlined below.
    The spectrum should not significantly differ between sample rates.
   - X3x0: 1, 5, 20, 33.333, 50, 66.666, 100, 200 MHz
-  - E3x0: 0.1, 0.5, 1, 1.143, 1.684 MHz
+  - E3xx: 0.1, 0.5, 1, 1.143, 1.684 MHz
 6. Repeat on each TX channel of the device
 7. This test fails if:
   - DC offset and IQ imbalance tones are unusually large
@@ -326,6 +342,7 @@ tbd
 | FPGAFUNCVERIF-N310-XG-v1  | USRP N310     | None        | \ref rdtesting_fpgafuncverif_manual | \ref rdtesting_fpgafuncverif_auto |
 | FPGAFUNCVERIF-N300-HG-v1  | USRP N300     | None        | \ref rdtesting_fpgafuncverif_manual | \ref rdtesting_fpgafuncverif_auto |
 | FPGAFUNCVERIF-N300-XG-v1  | USRP N300     | None        | \ref rdtesting_fpgafuncverif_manual | \ref rdtesting_fpgafuncverif_auto |
+| FPGAFUNCVERIF-E320-XG-v1  | USRP E320     | None        | \ref rdtesting_fpgafuncverif_manual | \ref rdtesting_fpgafuncverif_auto |
 
 The FPGA functional verification tests exercise the Digital Downconverter (DDC),
 Digital Upconverter (DUC), and Radio Core RFNoC blocks.
@@ -339,6 +356,7 @@ Digital Upconverter (DUC), and Radio Core RFNoC blocks.
   - 1 GigE and PCIe adapters and cabling for optional tests
 - E310: SG1 & SG3 with SSH access
 - N310: No special requirements
+- E320: SFP connection to run network mode
 
 \subsection rdtesting_fpgafuncverif_manual FPGA Functional Verification: Manual Test Procedure
 
@@ -413,7 +431,26 @@ rates and channel configurations without any data flow issues.
 
 Note: On TX tests, initial Us within the first 5 seconds can be ignored and do not fail the test
 
-#### USRP E3xx (SG3 Required, SG1 Optional)
+#### USRP E31x (SG3 Required, SG1 Optional)
+
+| Channels      | Master Clock Rate       | Sample Rate | Duration | Notes              |
+|---------------|-------------------------|-------------|----------|--------------------|
+| 1x RX         | 10e6                    | 1e6         | 60       | Test both channels |
+| 1x RX         | 61.44e6                 | 1.024e6     | 60       | Test both channels |
+| 1x TX         | 10e6                    | 1e6         | 60       | Test both channels |
+| 1x TX         | 61.44e6                 | 1.024e6     | 60       | Test both channels |
+| 2x RX         | 10e6                    | 1e6         | 60       |                    |
+| 2x RX         | 30.72e6                 | 1.024e6     | 60       |                    |
+| 2x TX         | 10e6                    | 1e6         | 60       |                    |
+| 2x TX         | 30.72e6                 | 1.024e6     | 60       |                    |
+| 1x RX & 1x TX | 10e6                    | 1e6         | 60       | Test both channels |
+| 1x RX & 1x TX | 61.44e6                 | 1.024e6     | 60       | Use channel 1      |
+| 2x RX & 2x TX | 10e6                    | 1e6         | 60       |                    |
+| 2x RX & 2x TX | 30.72e6                 | 1.024e6     | 60       |                    |
+| 1x RX & 1x TX | 61.44e6                 | 1e6         | 3600     | Use channel 0      |
+| 2x RX & 2x TX | 30.72e6                 | 1e6         | 3600     |                    |
+
+#### USRP E320: 1 GigE Interface
 
 | Channels      | Master Clock Rate       | Sample Rate | Duration | Notes              |
 |---------------|-------------------------|-------------|----------|--------------------|
@@ -432,6 +469,19 @@ Note: On TX tests, initial Us within the first 5 seconds can be ignored and do n
 | 1x RX & 1x TX | 61.44e6                 | 1e6         | 3600     | Use channel 0      |
 | 2x RX & 2x TX | 30.72e6                 | 1e6         | 3600     |                    |
 
+#### USRP E320: 10 GigE Interface
+
+| Channels      | Master Clock Rate       | Sample Rate          | Duration | Notes              |
+|---------------|-------------------------|----------------------|----------|--------------------|
+| 1x RX         | 61.44e6                 | 1.024e6, 61.44e6     | 60       | Test both channels |
+| 1x TX         | 61.44e6                 | 1.024e6, 61.44e6     | 60       | Test both channels |
+| 2x RX         | 30.72e6                 | 1.024e6, 30.72e6     | 60       |                    |
+| 2x TX         | 30.72e6                 | 1.024e6, 30.72e6     | 60       |                    |
+| 1x RX & 1x TX | 61.44e6                 | 1.024e6, 30.72e6     | 60       | Test both channels |
+| 2x RX & 2x TX | 30.72e6                 | 1.024e6, 30.72e6     | 60       |                    |
+| 1x RX & 1x TX | 61.44e6                 | 1e6, 30.72e6         | 3600     | Use channel 0      |
+| 2x RX & 2x TX | 30.72e6                 | 1e6, 30.72e6         | 3600     |                    |
+
 #### USRP N300/N310: 1 GigE Interface
 
 - Required images to test: HG
@@ -504,7 +554,7 @@ optimization), and that all NIC and kernel are set to optimal (CPU governor,
 ring buffer settings, ...).
 
 ### X310/X300
-The X310/X300 tests depend on the FPGA image to be tested. 
+The X310/X300 tests depend on the FPGA image to be tested.
 
 #### HG
 -Connect a 1GigE cable into port 0 and a 10GigE cable into port 1.
@@ -560,6 +610,22 @@ appropriate.
 
          $ usrp_fpga_funcverif n310wx -a 192.168.20.2 -p /path/to/examples
 
+### E320
+The E320 tests depend on the FPGA image to be tested.
+
+#### 1G
+- Connect a 1GigE cable on the SFP port.
+- The following command must pass:
+
+         $ usrp_fpga_funcverif e3201g -a 192.168.10.2 -p /path/to/examples
+
+#### XG
+- Connect a 10GigE cable on the SFP port.
+- The following command must pass:
+
+         $ usrp_fpga_funcverif e320xg -a 192.168.10.2 -p /path/to/examples
+
+
 \section rdtesting_phasealignment Phase alignment tests
 
 | Test Code           | Device    | Peripherals        | Manual Test Procedure                | Automatic Test Procedure    |
@@ -646,10 +712,11 @@ tbd
 
 \section rdtesting_bist BISTs
 
-| Test Code           | Device    | Peripherals         | Manual Test Procedure           | Automatic Test Procedure      |
-|---------------------|-----------|---------------------|---------------------------------|-------------------------------|
-| BIST-N310-v1        | 1xN310    | DB-15 GPIO Loopback | \ref rdtesting_bist_n3x0_manual | \ref rdtesting_bist_n3x0_auto |
-| BIST-N300-v1        | 1xN300    | DB-15 GPIO Loopback | \ref rdtesting_bist_n3x0_manual | \ref rdtesting_bist_n3x0_auto |
+| Test Code           | Device    | Peripherals                                           | Manual Test Procedure           | Automatic Test Procedure      |
+|---------------------|-----------|-------------------------------------------------------|---------------------------------|-------------------------------|
+| BIST-N310-v1        | 1xN310    | DB-15 GPIO Loopback                                   | \ref rdtesting_bist_n3x0_manual | \ref rdtesting_bist_n3x0_auto |
+| BIST-N300-v1        | 1xN300    | DB-15 GPIO Loopback                                   | \ref rdtesting_bist_n3x0_manual | \ref rdtesting_bist_n3x0_auto |
+| BIST-E320-v1        | 1xE320    | Type C HDMI Cable + Breakout board with GPIO Loopback | \ref rdtesting_bist_e320_manual | \ref rdtesting_bist_e320_auto |
 
 Some of our devices have built-in self-tests (BISTs).
 
@@ -658,7 +725,7 @@ Some of our devices have built-in self-tests (BISTs).
 Note: The N300 and N310 have identical BISTs.
 
 1. Connect the front-panel GPIO loopback to the front panel
-   (see \ref rdtesting_peripherals_gpiolb)
+   (see \ref rdtesting_n3xx_peripherals_gpiolb)
 2. Execute the following commands:
 
         $ n3xx_bist standard # Note: This will run multiple tests
@@ -701,9 +768,9 @@ plugged in, the test can trivially be executed automatically by running
 
 and making sure that all return values are 0.
 
-\section rdtesting_peripherals Required Peripherals
+\section rdtesting_n3xx_peripherals Required Peripherals
 
-\section rdtesting_peripherals_gpiolb DB15 GPIO Loopback
+\section rdtesting_n3xx_peripherals_gpiolb DB15 GPIO Loopback
 
 This is a cable or breakout board which connects to the DB15 connector and loops
 back the following pins:
@@ -715,6 +782,47 @@ back the following pins:
 - 4<->10
 - 5<->11
 
+\subsection rdtesting_bist_e320_manual E320 Manual Procedure
+
+1. Connect the front-panel GPIO loopback to the front panel
+   (see \ref rdtesting_e320_peripherals_gpiolb)
+2. Execute the following commands:
+
+        $ e320_bist standard # Note: This will run multiple tests
+        $ e320_bist gpio
+
+3. The final BIST is the SFP test. Connect an SFP loopback module
+   to the SFP port. Run the command:
+
+        $ e320_bist sfp_loopback
+
+Every test will produce a JSON-serialized dictionary. All tests have passed if
+the "status" key is "true", or the return code for `e320_bist` is 0.
+
+\subsection rdtesting_bist_e320_auto E320 Automatic Procedure
+
+Assuming the peripherals described in \ref rdtesting_bist_e320_manual are all
+plugged in, the test can trivially be executed automatically by running
+
+        $ e320_bist standard
+        $ e320_bist gpio
+        $ e320_bist sfp_loopback
+
+and making sure that all return values are 0.
+
+\section rdtesting_e320_peripherals Required Peripherals
+
+\section rdtesting_e320_peripherals_gpiolb  GPIO Loopback
+
+1. Type C to Type A HDMI Cable
+2. Breakout Board which connects to the connector and loops
+back the following pins:
+
+- 0<->4
+- 1<->5
+- 2<->6
+- 3<->7
+
 \section rdtesting_defining Defining R&D Tests
 
 Tests can be added any time to define procedures for pass/fail validation. Any