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| author | mattprost <matt.prost@ni.com> | 2020-04-07 09:53:38 -0500 |
|---|---|---|
| committer | Aaron Rossetto <aaron.rossetto@ni.com> | 2020-04-07 10:13:25 -0500 |
| commit | 002a787258f91095ea34d5ff362767fa0c6dc480 (patch) | |
| tree | 8cee6790c22e794fbb0bb141b23faa23a165d016 /host | |
| parent | d9f4d540ef334013eb404ce91b3b446e5fc917ff (diff) | |
| download | uhd-002a787258f91095ea34d5ff362767fa0c6dc480.tar.gz uhd-002a787258f91095ea34d5ff362767fa0c6dc480.tar.bz2 uhd-002a787258f91095ea34d5ff362767fa0c6dc480.zip | |
fixup! rfnoc: Use multichannel register interface for RFNoC blocks
Diffstat (limited to 'host')
| -rw-r--r-- | host/lib/rfnoc/ddc_block_control.cpp | 6 | ||||
| -rw-r--r-- | host/lib/rfnoc/duc_block_control.cpp | 6 | ||||
| -rw-r--r-- | host/lib/rfnoc/radio_control_impl.cpp | 6 |
3 files changed, 9 insertions, 9 deletions
diff --git a/host/lib/rfnoc/ddc_block_control.cpp b/host/lib/rfnoc/ddc_block_control.cpp index a35d750ff..0522991ba 100644 --- a/host/lib/rfnoc/ddc_block_control.cpp +++ b/host/lib/rfnoc/ddc_block_control.cpp @@ -54,11 +54,11 @@ class ddc_block_control_impl : public ddc_block_control { public: RFNOC_BLOCK_CONSTRUCTOR(ddc_block_control) - , _fpga_compat(regs().peek32(RB_COMPAT_NUM)), + , _ddc_reg_iface(*this, 0, REG_CHAN_OFFSET), + _fpga_compat(regs().peek32(RB_COMPAT_NUM)), _num_halfbands(regs().peek32(RB_NUM_HB)), _cic_max_decim(regs().peek32(RB_CIC_MAX_DECIM)), - _residual_scaling(get_num_input_ports(), DEFAULT_SCALING), - _ddc_reg_iface(*this, 0, REG_CHAN_OFFSET) + _residual_scaling(get_num_input_ports(), DEFAULT_SCALING) { UHD_ASSERT_THROW(get_num_input_ports() == get_num_output_ports()); UHD_ASSERT_THROW(_cic_max_decim > 0 && _cic_max_decim <= 0xFF); diff --git a/host/lib/rfnoc/duc_block_control.cpp b/host/lib/rfnoc/duc_block_control.cpp index 1795a275a..6b052e17a 100644 --- a/host/lib/rfnoc/duc_block_control.cpp +++ b/host/lib/rfnoc/duc_block_control.cpp @@ -52,11 +52,11 @@ class duc_block_control_impl : public duc_block_control { public: RFNOC_BLOCK_CONSTRUCTOR(duc_block_control) - , _fpga_compat(regs().peek32(RB_COMPAT_NUM)), + , _duc_reg_iface(*this, 0, REG_CHAN_OFFSET), + _fpga_compat(regs().peek32(RB_COMPAT_NUM)), _num_halfbands(regs().peek32(RB_NUM_HB)), _cic_max_interp(regs().peek32(RB_CIC_MAX_INTERP)), - _residual_scaling(get_num_input_ports(), DEFAULT_SCALING), - _duc_reg_iface(*this, 0, REG_CHAN_OFFSET) + _residual_scaling(get_num_input_ports(), DEFAULT_SCALING) { UHD_ASSERT_THROW(get_num_input_ports() == get_num_output_ports()); UHD_ASSERT_THROW(_cic_max_interp > 0 && _cic_max_interp <= 0xFF); diff --git a/host/lib/rfnoc/radio_control_impl.cpp b/host/lib/rfnoc/radio_control_impl.cpp index b5c3181a5..4f1246e5c 100644 --- a/host/lib/rfnoc/radio_control_impl.cpp +++ b/host/lib/rfnoc/radio_control_impl.cpp @@ -67,15 +67,15 @@ static constexpr double OVERRUN_RESTART_DELAY = 0.05; ***************************************************************************/ radio_control_impl::radio_control_impl(make_args_ptr make_args) : radio_control(std::move(make_args)) + , _radio_reg_iface(*this, + radio_control_impl::regmap::RADIO_BASE_ADDR, + radio_control_impl::regmap::REG_CHAN_OFFSET) , _fpga_compat(regs().peek32(regmap::REG_COMPAT_NUM)) , _radio_width(regs().peek32(regmap::REG_RADIO_WIDTH)) , _samp_width(_radio_width >> 16) , _spc(_radio_width & 0xFFFF) , _last_stream_cmd( get_num_output_ports(), uhd::stream_cmd_t::STREAM_MODE_STOP_CONTINUOUS) - , _radio_reg_iface(*this, - radio_control_impl::regmap::RADIO_BASE_ADDR, - radio_control_impl::regmap::REG_CHAN_OFFSET) { uhd::assert_fpga_compat(MAJOR_COMPAT, MINOR_COMPAT, |