DDC/DUC: switch CORDIC -> DDS for all relevant variable names

- Bump compat number for DDC/DUC to 2.0

10 files changed, 36 insertions, 40 deletions

diff --git a/host/include/uhd/rfnoc/blocks/ddc.xml b/host/include/uhd/rfnoc/blocks/ddc.xml
index 13b9414bd..43e325c0e 100644
--- a/host/include/uhd/rfnoc/blocks/ddc.xml
+++ b/host/include/uhd/rfnoc/blocks/ddc.xml
@@ -25,8 +25,8 @@
     </setreg>
     <!-- DDC block registers -->
     <setreg>
-      <!-- CORDIC phase increment word -->
-      <name>CORDIC_FREQ</name>
+      <!-- DDS phase increment word -->
+      <name>DDS_FREQ</name>
       <address>132</address>
     </setreg>
     <setreg>
diff --git a/host/include/uhd/rfnoc/blocks/ddc_single.xml b/host/include/uhd/rfnoc/blocks/ddc_single.xml
index 581487388..1843adb5b 100644
--- a/host/include/uhd/rfnoc/blocks/ddc_single.xml
+++ b/host/include/uhd/rfnoc/blocks/ddc_single.xml
@@ -25,8 +25,8 @@
     </setreg>
     <!-- DDC block registers -->
     <setreg>
-      <!-- CORDIC phase increment word -->
-      <name>CORDIC_FREQ</name>
+      <!-- DDS phase increment word -->
+      <name>DDS_FREQ</name>
       <address>132</address>
     </setreg>
     <setreg>
diff --git a/host/include/uhd/rfnoc/blocks/duc.xml b/host/include/uhd/rfnoc/blocks/duc.xml
index 9be54da78..ea83942da 100644
--- a/host/include/uhd/rfnoc/blocks/duc.xml
+++ b/host/include/uhd/rfnoc/blocks/duc.xml
@@ -29,7 +29,7 @@
       <address>131</address>
     </setreg>
     <setreg>
-      <name>CORDIC_FREQ</name>
+      <name>DDS_FREQ</name>
       <address>132</address>
     </setreg>
     <setreg>
diff --git a/host/include/uhd/rfnoc/blocks/duc_single.xml b/host/include/uhd/rfnoc/blocks/duc_single.xml
index 39038eeee..235788989 100644
--- a/host/include/uhd/rfnoc/blocks/duc_single.xml
+++ b/host/include/uhd/rfnoc/blocks/duc_single.xml
@@ -29,7 +29,7 @@
       <address>131</address>
     </setreg>
     <setreg>
-      <name>CORDIC_FREQ</name>
+      <name>DDS_FREQ</name>
       <address>132</address>
     </setreg>
     <setreg>
diff --git a/host/lib/include/uhdlib/usrp/cores/rx_dsp_core_3000.hpp b/host/lib/include/uhdlib/usrp/cores/rx_dsp_core_3000.hpp
index 0fba8ed65..8ea4531a1 100644
--- a/host/lib/include/uhdlib/usrp/cores/rx_dsp_core_3000.hpp
+++ b/host/lib/include/uhdlib/usrp/cores/rx_dsp_core_3000.hpp
@@ -22,6 +22,7 @@
 class rx_dsp_core_3000 : boost::noncopyable{
 public:
     static const double DEFAULT_CORDIC_FREQ;
+    static const double DEFAULT_DDS_FREQ;
     static const double DEFAULT_RATE;
 
     typedef boost::shared_ptr<rx_dsp_core_3000> sptr;
diff --git a/host/lib/include/uhdlib/usrp/cores/tx_dsp_core_3000.hpp b/host/lib/include/uhdlib/usrp/cores/tx_dsp_core_3000.hpp
index 3eb53da0d..d63f6a609 100644
--- a/host/lib/include/uhdlib/usrp/cores/tx_dsp_core_3000.hpp
+++ b/host/lib/include/uhdlib/usrp/cores/tx_dsp_core_3000.hpp
@@ -19,6 +19,7 @@
 class tx_dsp_core_3000 : boost::noncopyable{
 public:
     static const double DEFAULT_CORDIC_FREQ;
+    static const double DEFAULT_DDS_FREQ;
     static const double DEFAULT_RATE;
 
     typedef boost::shared_ptr<tx_dsp_core_3000> sptr;
diff --git a/host/lib/rfnoc/ddc_block_ctrl_impl.cpp b/host/lib/rfnoc/ddc_block_ctrl_impl.cpp
index 2919c163b..9247708ef 100644
--- a/host/lib/rfnoc/ddc_block_ctrl_impl.cpp
+++ b/host/lib/rfnoc/ddc_block_ctrl_impl.cpp
@@ -197,7 +197,7 @@ public:
     }
 
 private:
-    static constexpr size_t MAJOR_COMP = 1;
+    static constexpr size_t MAJOR_COMP = 2;
     static constexpr size_t MINOR_COMP = 0;
     static constexpr size_t RB_REG_COMPAT_NUM = 0;
     static constexpr size_t RB_REG_NUM_HALFBANDS = 1;
@@ -207,18 +207,18 @@ private:
     const size_t _num_halfbands;
     const size_t _cic_max_decim;
 
-    //! Set the CORDIC frequency shift the signal to \p requested_freq
+    //! Set the DDS frequency shift the signal to \p requested_freq
     double set_freq(const double requested_freq, const size_t chan)
     {
         const double input_rate = get_arg<double>("input_rate");
         double actual_freq;
         int32_t freq_word;
         get_freq_and_freq_word(requested_freq, input_rate, actual_freq, freq_word);
-        sr_write("CORDIC_FREQ", uint32_t(freq_word), chan);
+        sr_write("DDS_FREQ", uint32_t(freq_word), chan);
         return actual_freq;
     }
 
-    //! Return a range of valid frequencies the CORDIC can tune to
+    //! Return a range of valid frequencies the DDS can tune to
     uhd::meta_range_t get_freq_range(void)
     {
         const double input_rate = get_arg<double>("input_rate");
@@ -286,19 +286,17 @@ private:
         // Calculate algorithmic gain of CIC for a given decimation.
         // For Ettus CIC R=decim, M=1, N=4. Gain = (R * M) ^ N
         const double rate_pow = std::pow(double(decim & 0xff), 4);
-        // Calculate compensation gain values for algorithmic gain of CORDIC and CIC taking into account
+        // Calculate compensation gain values for algorithmic gain of DDS and CIC taking into account
         // gain compensation blocks already hardcoded in place in DDC (that provide simple 1/2^n gain compensation).
-        // CORDIC algorithmic gain limits asymptotically around 1.647 after many iterations.
-        static const double CORDIC_GAIN = 1.648;
+        static const double DDS_GAIN = 2.0;
         //
         // The polar rotation of [I,Q] = [1,1] by Pi/8 also yields max magnitude of SQRT(2) (~1.4142) however
-        // input to the CORDIC thats outside the unit circle can only be sourced from a saturated RF frontend.
+        // input to the DDS thats outside the unit circle can only be sourced from a saturated RF frontend.
         // To provide additional dynamic range head room accordingly using scale factor applied at egress from DDC would
         // cost us small signal performance, thus we do no provide compensation gain for a saturated front end and allow
         // the signal to clip in the H/W as needed. If we wished to avoid the signal clipping in these circumstances then adjust code to read:
-        // _scaling_adjustment = std::pow(2, ceil_log2(rate_pow))/(CORDIC_GAIN*rate_pow*1.415);
         const double scaling_adjustment =
-            std::pow(2, uhd::math::ceil_log2(rate_pow))/(CORDIC_GAIN*rate_pow);
+            std::pow(2, uhd::math::ceil_log2(rate_pow))/(DDS_GAIN*rate_pow);
         update_scalar(scaling_adjustment, chan);
         return input_rate/decim_rate;
     }
@@ -312,7 +310,7 @@ private:
         set_arg<double>("output_rate", desired_output_rate, chan);
     }
 
-    // Calculate compensation gain values for algorithmic gain of CORDIC and CIC taking into account
+    // Calculate compensation gain values for algorithmic gain of DDS and CIC taking into account
     // gain compensation blocks already hardcoded in place in DDC (that provide simple 1/2^n gain compensation).
     // Further more factor in OTW format which adds further gain factor to weight output samples correctly.
     void update_scalar(const double scalar, const size_t chan)
@@ -324,7 +322,7 @@ private:
             target_scalar / actual_scalar / double(1 << 15) // Rounding error, normalized to 1.0
             * get_arg<double>("fullscale"); // Scaling requested by host
         set_arg<double>("scalar_correction", scalar_correction, chan);
-        // Write DDC with scaling correction for CIC and CORDIC that maximizes dynamic range in 32/16/12/8bits.
+        // Write DDC with scaling correction for CIC and DDS that maximizes dynamic range in 32/16/12/8bits.
         sr_write("SCALE_IQ", actual_scalar, chan);
     }
 
diff --git a/host/lib/rfnoc/duc_block_ctrl_impl.cpp b/host/lib/rfnoc/duc_block_ctrl_impl.cpp
index 68109ec26..7f22ca903 100644
--- a/host/lib/rfnoc/duc_block_ctrl_impl.cpp
+++ b/host/lib/rfnoc/duc_block_ctrl_impl.cpp
@@ -182,7 +182,7 @@ public:
 
 private:
 
-    static constexpr size_t MAJOR_COMP = 1;
+    static constexpr size_t MAJOR_COMP = 2;
     static constexpr size_t MINOR_COMP = 0;
     static constexpr size_t RB_REG_COMPAT_NUM = 0;
     static constexpr size_t RB_REG_NUM_HALFBANDS = 1;
@@ -192,19 +192,18 @@ private:
     const size_t _num_halfbands;
     const size_t _cic_max_interp;
 
-    //! Set the CORDIC frequency shift the signal to \p requested_freq
+    //! Set the DDS frequency shift the signal to \p requested_freq
     double set_freq(const double requested_freq, const size_t chan)
     {
         const double output_rate = get_arg<double>("output_rate");
         double actual_freq;
         int32_t freq_word;
         get_freq_and_freq_word(requested_freq, output_rate, actual_freq, freq_word);
-        // Xilinx CORDIC uses a different format for the phase increment, hence the divide-by-four:
-        sr_write("CORDIC_FREQ", uint32_t(freq_word/4), chan);
+        sr_write("DDS_FREQ", uint32_t(freq_word), chan);
         return actual_freq;
     }
 
-    //! Return a range of valid frequencies the CORDIC can tune to
+    //! Return a range of valid frequencies the DDS can tune to
     uhd::meta_range_t get_freq_range(void)
     {
         const double output_rate = get_arg<double>("output_rate");
@@ -263,10 +262,7 @@ private:
         // For Ettus CIC R=interp, M=1, N=4. Gain = (R * M) ^ (N - 1)
         const int CIC_N = 4;
         const double rate_pow = std::pow(double(interp & 0xff), CIC_N - 1);
-
-        // Experimentally determined value to scale the output to [-1, 1]
-        // This must also encompass the CORDIC gain
-        static const double CONSTANT_GAIN = 1.1644;
+        const double CONSTANT_GAIN = 1.0;
 
         const double scaling_adjustment =
             std::pow(2, uhd::math::ceil_log2(rate_pow))/(CONSTANT_GAIN*rate_pow);
@@ -283,7 +279,7 @@ private:
         set_arg<double>("input_rate", desired_input_rate, chan);
     }
 
-    // Calculate compensation gain values for algorithmic gain of CORDIC and CIC taking into account
+    // Calculate compensation gain values for algorithmic gain of DDS and CIC taking into account
     // gain compensation blocks already hardcoded in place in DUC (that provide simple 1/2^n gain compensation).
     // Further more factor in OTW format which adds further gain factor to weight output samples correctly.
     void update_scalar(const double scalar, const size_t chan)
diff --git a/host/lib/usrp/cores/rx_dsp_core_3000.cpp b/host/lib/usrp/cores/rx_dsp_core_3000.cpp
index 27fc760af..c7d3c25c8 100644
--- a/host/lib/usrp/cores/rx_dsp_core_3000.cpp
+++ b/host/lib/usrp/cores/rx_dsp_core_3000.cpp
@@ -37,6 +37,7 @@ template <class T> T ceil_log2(T num){
 using namespace uhd;
 
 const double rx_dsp_core_3000::DEFAULT_CORDIC_FREQ = 0.0;
+const double rx_dsp_core_3000::DEFAULT_DDS_FREQ = 0.0;
 const double rx_dsp_core_3000::DEFAULT_RATE = 1e6;
 
 rx_dsp_core_3000::~rx_dsp_core_3000(void){
@@ -191,24 +192,23 @@ public:
         // Caclulate algorithmic gain of CIC for a given decimation.
         // For Ettus CIC R=decim, M=1, N=4. Gain = (R * M) ^ N
         const double rate_pow = std::pow(double(decim & 0xff), 4);
-        // Calculate compensation gain values for algorithmic gain of CORDIC and CIC taking into account
+        // Calculate compensation gain values for algorithmic gain of and CIC taking into account
         // gain compensation blocks already hardcoded in place in DDC (that provide simple 1/2^n gain compensation).
-        // CORDIC algorithmic gain limits asymptotically around 1.647 after many iterations.
         //
         // The polar rotation of [I,Q] = [1,1] by Pi/8 also yields max magnitude of SQRT(2) (~1.4142) however
-        // input to the CORDIC thats outside the unit circle can only be sourced from a saturated RF frontend.
+        // input to the DDS thats outside the unit circle can only be sourced from a saturated RF frontend.
         // To provide additional dynamic range head room accordingly using scale factor applied at egress from DDC would
         // cost us small signal performance, thus we do no provide compensation gain for a saturated front end and allow
         // the signal to clip in the H/W as needed. If we wished to avoid the signal clipping in these circumstances then adjust code to read:
         // _scaling_adjustment = std::pow(2, ceil_log2(rate_pow))/(1.648*rate_pow*1.415);
-        _scaling_adjustment = std::pow(2, ceil_log2(rate_pow))/(1.648*rate_pow);
+        _scaling_adjustment = std::pow(2, ceil_log2(rate_pow))/(2.0*rate_pow);
 
         this->update_scalar();
 
         return _tick_rate/decim_rate;
     }
 
-    // Calculate compensation gain values for algorithmic gain of CORDIC and CIC taking into account
+    // Calculate compensation gain values for algorithmic gain of DDS and CIC taking into account
     // gain compensation blocks already hardcoded in place in DDC (that provide simple 1/2^n gain compensation).
     // Further more factor in OTW format which adds further gain factor to weight output samples correctly.
     void update_scalar(void){
@@ -216,7 +216,7 @@ public:
         const int32_t actual_scalar = boost::math::iround(target_scalar);
         // Calculate the error introduced by using integer representation for the scalar, can be corrected in host later.
         _fxpt_scalar_correction = target_scalar/actual_scalar;
-        // Write DDC with scaling correction for CIC and CORDIC that maximizes dynamic range in 32/16/12/8bits.
+        // Write DDC with scaling correction for CIC and DDS that maximizes dynamic range in 32/16/12/8bits.
         _iface->poke32(REG_DSP_RX_SCALE_IQ, actual_scalar);
     }
 
@@ -277,7 +277,7 @@ public:
             .set_coercer(boost::bind(&rx_dsp_core_3000::set_host_rate, this, _1))
         ;
         subtree->create<double>("freq/value")
-            .set(DEFAULT_CORDIC_FREQ)
+            .set(DEFAULT_DDS_FREQ)
             .set_coercer(boost::bind(&rx_dsp_core_3000::set_freq, this, _1))
         ;
         subtree->create<meta_range_t>("freq/range")
diff --git a/host/lib/usrp/cores/tx_dsp_core_3000.cpp b/host/lib/usrp/cores/tx_dsp_core_3000.cpp
index b04a20497..cc4d23393 100644
--- a/host/lib/usrp/cores/tx_dsp_core_3000.cpp
+++ b/host/lib/usrp/cores/tx_dsp_core_3000.cpp
@@ -28,6 +28,7 @@ template <class T> T ceil_log2(T num){
 using namespace uhd;
 
 const double tx_dsp_core_3000::DEFAULT_CORDIC_FREQ = 0.0;
+const double tx_dsp_core_3000::DEFAULT_DDS_FREQ = 0.0;
 const double tx_dsp_core_3000::DEFAULT_RATE = 1e6;
 
 tx_dsp_core_3000::~tx_dsp_core_3000(void){
@@ -103,16 +104,15 @@ public:
         // Caclulate algorithmic gain of CIC for a given interpolation
         // For Ettus CIC R=decim, M=1, N=3. Gain = (R * M) ^ N
         const double rate_pow = std::pow(double(interp & 0xff), 3);
-        // Calculate compensation gain values for algorithmic gain of CORDIC and CIC taking into account
+        // Calculate compensation gain values for algorithmic gain of DDS and CIC taking into account
         // gain compensation blocks already hardcoded in place in DDC (that provide simple 1/2^n gain compensation).
-        // CORDIC algorithmic gain limits asymptotically around 1.647 after many iterations.
-        _scaling_adjustment = std::pow(2, ceil_log2(rate_pow))/(1.648*rate_pow);
+        _scaling_adjustment = std::pow(2, ceil_log2(rate_pow))/(rate_pow);
         this->update_scalar();
 
         return _tick_rate/interp_rate;
     }
 
-  // Calculate compensation gain values for algorithmic gain of CORDIC and CIC taking into account
+  // Calculate compensation gain values for algorithmic gain of DDS and CIC taking into account
   // gain compensation blocks already hardcoded in place in DDC (that provide simple 1/2^n gain compensation).
   // Further more factor in OTW format which adds further gain factor to weight output samples correctly.
     void update_scalar(void){
@@ -177,7 +177,7 @@ public:
             .set_coercer(boost::bind(&tx_dsp_core_3000::set_host_rate, this, _1))
         ;
         subtree->create<double>("freq/value")
-            .set(DEFAULT_CORDIC_FREQ)
+            .set(DEFAULT_DDS_FREQ)
             .set_coercer(boost::bind(&tx_dsp_core_3000::set_freq, this, _1))
         ;
         subtree->create<meta_range_t>("freq/range")