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authorMartin Braun <martin.braun@ettus.com>2019-01-11 13:39:55 -0800
committerBrent Stapleton <brent.stapleton@ettus.com>2019-01-15 11:43:11 -0800
commit853c2a2263e54c1e1fd9562b479a17122a6d9b37 (patch)
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docs: Add comments for TwinRX and MCR
The TwinRX dboards only support a master clock rate of 200 MHz, which is now emphasized in the manual. In addition, the meaning of tick rate, sampling rate, and master clock rate in the TwinRX context is explained.
Diffstat (limited to 'host')
-rw-r--r--host/docs/dboards.dox3
-rw-r--r--host/docs/twinrx.dox22
2 files changed, 25 insertions, 0 deletions
diff --git a/host/docs/dboards.dox b/host/docs/dboards.dox
index 0ab5927a6..dfeadf0ed 100644
--- a/host/docs/dboards.dox
+++ b/host/docs/dboards.dox
@@ -384,6 +384,9 @@ Receive Antennas: **RX1** and **RX2**
Receive Gain: 0-93dB
+The TwinRX daughterboard only works with the X300/X310 motherboards, and
+requires a master clock rate of 200 MHz.
+
More information:
\li \subpage page_twinrx
diff --git a/host/docs/twinrx.dox b/host/docs/twinrx.dox
index c85b78b4c..cc7f8f3a1 100644
--- a/host/docs/twinrx.dox
+++ b/host/docs/twinrx.dox
@@ -14,6 +14,28 @@ communication with a combined bandwidth of 160 MHz. The ability to share the LO
daughterboards enables the phase-aligned operation required to implement scalable multi-channel phased-arrays.
The receiver is capable of fast frequency hopping to detect frequency agile emitters.
+The TwinRX daughterboard only works with the X300/X310 series of USRPs.
+
+\subsection twinrx_dboards_mcr Master Clock Rate, Sampling Rate, and Tick Rate
+
+Due to the specific configuration of the analog filters, the TwinRX can only
+support a master clock rate of 200 MHz. Since the X310/X300 only has a single
+master clock, this means that the only valid tick rate for the X300/X310 is
+200 MHz, even if there is another daughterboard in the same device which could
+support a different tick rate.
+
+The TwinRX uses the dual-ADC of each X300 channel to sample two separate IF
+streams, thus enabling two receive channels where there usually only is one.
+Every IF channel is sampled at 200 MHz (real sampling), and then converted to
+a 100 Msps complex sample stream per channel. This means the total output of
+one daughterboard is 2x100 Msps, which is the same aggregate sampling rate as
+with single-channel daughterboards such as the UBX.
+
+The tick rate is then also halved to match the sampling rate. Timed commands
+are executed relative to a sample edge in the I/Q domain, i.e., at a granularity
+of 1/100 MHz = 10 ns.
+
+
\image html TwinRX_Block_Diagram.png "TwinRX Block Diagram"
\subsection twinrx_frequency_bands Frequency Bands