diff options
author | Martin Braun <martin.braun@ettus.com> | 2014-11-21 15:27:36 +0100 |
---|---|---|
committer | Martin Braun <martin.braun@ettus.com> | 2014-11-21 15:27:36 +0100 |
commit | 7866b66587c7570890a24a7ebc89330976a8d81b (patch) | |
tree | 35bc650e3364802be610f150a2a6d9c85511899d /host | |
parent | acb76266a9470209128dcfe982bfd33c1545df97 (diff) | |
download | uhd-7866b66587c7570890a24a7ebc89330976a8d81b.tar.gz uhd-7866b66587c7570890a24a7ebc89330976a8d81b.tar.bz2 uhd-7866b66587c7570890a24a7ebc89330976a8d81b.zip |
docs: Added notes on auto_tick_rate (B200)
Diffstat (limited to 'host')
-rw-r--r-- | host/docs/usrp_b200.dox | 31 | ||||
-rw-r--r-- | host/include/uhd/usrp/multi_usrp.hpp | 5 |
2 files changed, 33 insertions, 3 deletions
diff --git a/host/docs/usrp_b200.dox b/host/docs/usrp_b200.dox index 6ee2f3445..9d3550b98 100644 --- a/host/docs/usrp_b200.dox +++ b/host/docs/usrp_b200.dox @@ -36,15 +36,40 @@ images: The master clock rate feeds the RF frontends and the DSP chains. Users may select non-default clock rates to acheive integer decimations or -interpolations in the DSP chains. The default master clock rate defaults -to 32 MHz, but can be set to any rate between 5 MHz and 61.44 MHz. +interpolations in the DSP chains. The clock rate can be set to any value +between 5 MHz and 61.44 MHz (or 30.72 MHz for dual-channel mode). +Note that rates above 56 MHz are possible, but not recommended. The user can set the master clock rate through the usrp API call uhd::usrp::multi_usrp::set_master_clock_rate(), or the clock rate can be set through the -device arguments, which many applications take: : +device arguments, which many applications take: uhd_usrp_probe --args="master_clock_rate=52e6" +The property to control the master clock rate is a double value, called `tick_rate`. + +\subsection b200_auto_mcr Automatic Clock Rate Setting + +The default clock rate setting is to automatically set a clock rate +depending on the requested sampling rate. The automatic clock rate selection +is disabled when either `master_clock_rate` is given in the device initialization +arguments, or when uhd::usrp::multi_usrp::set_master_clock_rate() is called. + +Note that the master clock rate must be an integer multiple of the sampling +rate. If a master clock rate is chosen for which this condition does not +hold, a warning will be displayed and a different sampling rate is used internally. + +Nevertheless, there are multiple valid values for the master clock rate +for most sampling rates. The auto clock rate selection attempts to use +the largest possible clock rate as to enable as many half-band filters +as possible. Expert users might have cases where a more fine-grained +control over the resampling stages is required, in which case manually +selecting a master clock rate might be more suitable than the automatic +rate. + +The property to dis- or enable the auto tick rate is a boolean value, +`auto_tick_rate`. + \section b200_fe RF Frontend Notes The B200 features an integrated RF frontend. diff --git a/host/include/uhd/usrp/multi_usrp.hpp b/host/include/uhd/usrp/multi_usrp.hpp index 6fd22ff23..2362ebcd7 100644 --- a/host/include/uhd/usrp/multi_usrp.hpp +++ b/host/include/uhd/usrp/multi_usrp.hpp @@ -155,6 +155,11 @@ public: * If the specified rate is not available, this method will throw. * On other devices, this method notifies the software of the rate, * but requires the the user has made the necessary hardware change. + * + * If the device has an 'auto clock rate' setting (e.g. B200, see also + * \ref b200_auto_mcr), this will get disabled and the clock rate will be + * fixed to \p rate. + * * \param rate the new master clock rate in Hz * \param mboard the motherboard index 0 to M-1 */ |