uhd: Replace clocking_mode_t unscoped enum with scoped version

This is not a functional change, but it marks the usage of scoped enums
in UHD. Commits past this one may also use this C++11 feature.

5 files changed, 8 insertions, 8 deletions

diff --git a/host/lib/usrp/b200/b200_impl.cpp b/host/lib/usrp/b200/b200_impl.cpp
index 62f0c2f59..fd87cf24a 100644
--- a/host/lib/usrp/b200/b200_impl.cpp
+++ b/host/lib/usrp/b200/b200_impl.cpp
@@ -60,7 +60,7 @@ public:
         }
     }
     clocking_mode_t get_clocking_mode() {
-        return AD9361_XTAL_N_CLK_PATH;
+        return clocking_mode_t::AD9361_XTAL_N_CLK_PATH;
     }
     digital_interface_mode_t get_digital_interface_mode() {
         return AD9361_DDR_FDD_LVCMOS;
@@ -88,7 +88,7 @@ public:
         }
     }
     clocking_mode_t get_clocking_mode() {
-        return AD9361_XTAL_N_CLK_PATH;
+        return clocking_mode_t::AD9361_XTAL_N_CLK_PATH;
     }
     digital_interface_mode_t get_digital_interface_mode() {
         return AD9361_DDR_FDD_LVCMOS;
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_client.h b/host/lib/usrp/common/ad9361_driver/ad9361_client.h
index 921045fbd..4fea53521 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_client.h
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_client.h
@@ -34,10 +34,10 @@ typedef enum {
 /*!
  * Clocking mode
  */
-typedef enum {
+enum class clocking_mode_t {
     AD9361_XTAL_P_CLK_PATH,
     AD9361_XTAL_N_CLK_PATH
-} clocking_mode_t;
+};
 
 /*!
  * Digital interface specific
diff --git a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
index e2ed2c77d..110756eb5 100644
--- a/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
+++ b/host/lib/usrp/common/ad9361_driver/ad9361_device.cpp
@@ -1583,11 +1583,11 @@ void ad9361_device_t::initialize()
 
     /* Enable clocks. */
     switch (_client_params->get_clocking_mode()) {
-    case AD9361_XTAL_N_CLK_PATH: {
+    case clocking_mode_t::AD9361_XTAL_N_CLK_PATH: {
         _io_iface->poke8(0x009, 0x17);
     } break;
 
-    case AD9361_XTAL_P_CLK_PATH: {
+    case clocking_mode_t::AD9361_XTAL_P_CLK_PATH: {
         _io_iface->poke8(0x009, 0x07);
         _io_iface->poke8(0x292, 0x08);
         _io_iface->poke8(0x293, 0x80);
diff --git a/host/lib/usrp/e300/e300_defaults.hpp b/host/lib/usrp/e300/e300_defaults.hpp
index 267897e03..cc810c0df 100644
--- a/host/lib/usrp/e300/e300_defaults.hpp
+++ b/host/lib/usrp/e300/e300_defaults.hpp
@@ -60,7 +60,7 @@ public:
         }
     }
     clocking_mode_t get_clocking_mode() {
-        return AD9361_XTAL_N_CLK_PATH;
+        return clocking_mode_t::AD9361_XTAL_N_CLK_PATH;
     }
     digital_interface_mode_t get_digital_interface_mode() {
         return AD9361_DDR_FDD_LVCMOS;
diff --git a/host/lib/usrp/n230/n230_resource_manager.cpp b/host/lib/usrp/n230/n230_resource_manager.cpp
index e9bb9c2c5..08a98d245 100644
--- a/host/lib/usrp/n230/n230_resource_manager.cpp
+++ b/host/lib/usrp/n230/n230_resource_manager.cpp
@@ -58,7 +58,7 @@ public:
         }
     }
     clocking_mode_t get_clocking_mode() {
-        return AD9361_XTAL_N_CLK_PATH;
+        return clocking_mode_t::AD9361_XTAL_N_CLK_PATH;
     }
     digital_interface_mode_t get_digital_interface_mode() {
         return AD9361_DDR_FDD_LVDS;