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| author | michael-west <michael.west@ettus.com> | 2014-09-25 15:49:14 -0700 |
|---|---|---|
| committer | Martin Braun <martin.braun@ettus.com> | 2014-09-25 17:12:15 -0700 |
| commit | 9dc96fd9bf8d430a9f41f3476bc62cc3ba43e1d7 (patch) | |
| tree | 087e5011db976fccea5d1448acaf75a6cb26337a /host | |
| parent | b765df3b1976f30a8b95f5a1ea482517a8000a80 (diff) | |
| download | uhd-9dc96fd9bf8d430a9f41f3476bc62cc3ba43e1d7.tar.gz uhd-9dc96fd9bf8d430a9f41f3476bc62cc3ba43e1d7.tar.bz2 uhd-9dc96fd9bf8d430a9f41f3476bc62cc3ba43e1d7.zip | |
x300: Reverted back to no analog delay for DAC ref clocks
Diffstat (limited to 'host')
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index dbaa67592..9307c62f0 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -295,8 +295,6 @@ void set_master_clock_rate(double clock_rate) { // Register 3 _lmk04816_regs.CLKout6_7_DIV = vco_div; _lmk04816_regs.CLKout6_7_OSCin_Sel = lmk04816_regs_t::CLKOUT6_7_OSCIN_SEL_VCO; - _lmk04816_regs.CLKout6_ADLY_SEL = lmk04816_regs_t::CLKOUT6_ADLY_SEL_D_EV_X; - _lmk04816_regs.CLKout7_ADLY_SEL = lmk04816_regs_t::CLKOUT7_ADLY_SEL_D_EV_X; // Register 4 _lmk04816_regs.CLKout8_9_DIV = vco_div; // Register 5 @@ -318,9 +316,6 @@ void set_master_clock_rate(double clock_rate) { _lmk04816_regs.CLKout6_TYPE = lmk04816_regs_t::CLKOUT6_TYPE_LVPECL_700MVPP; //DB0_DAC _lmk04816_regs.CLKout7_TYPE = lmk04816_regs_t::CLKOUT7_TYPE_LVPECL_700MVPP; //DB1_DAC _lmk04816_regs.CLKout8_TYPE = lmk04816_regs_t::CLKOUT8_TYPE_LVPECL_700MVPP; //DB0_ADC - // Analog delay of 900ps to synchronize the DAC reference clocks with the source synchronous DAC clocks. - // This delay may need to vary due to temperature. Tested and verified at room temperature only. - _lmk04816_regs.CLKout6_7_ADLY = 0x10; // Register 8 _lmk04816_regs.CLKout9_TYPE = lmk04816_regs_t::CLKOUT9_TYPE_LVPECL_700MVPP; //DB1_ADC |