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| author | Ashish Chaudhari <ashish@ettus.com> | 2015-07-14 12:53:29 -0700 |
|---|---|---|
| committer | Ashish Chaudhari <ashish@ettus.com> | 2015-07-14 13:00:25 -0700 |
| commit | 8a76d46b1a4aed847e0a160d4f95c8a5e8792b62 (patch) | |
| tree | 956d2f4c0f1238d739262f6c5a94abfca60bd3ef /host | |
| parent | 8116ae2114079f0e1b868a198ceefb5f2a066ee9 (diff) | |
| download | uhd-8a76d46b1a4aed847e0a160d4f95c8a5e8792b62.tar.gz uhd-8a76d46b1a4aed847e0a160d4f95c8a5e8792b62.tar.bz2 uhd-8a76d46b1a4aed847e0a160d4f95c8a5e8792b62.zip | |
x300: Updated pre-rev7 board delays after characterization
- Characterized over process and temperature
Diffstat (limited to 'host')
| -rw-r--r-- | host/lib/usrp/x300/x300_clock_ctrl.cpp | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/host/lib/usrp/x300/x300_clock_ctrl.cpp b/host/lib/usrp/x300/x300_clock_ctrl.cpp index 266797bff..0812bcc8e 100644 --- a/host/lib/usrp/x300/x300_clock_ctrl.cpp +++ b/host/lib/usrp/x300/x300_clock_ctrl.cpp @@ -45,12 +45,11 @@ struct x300_clk_delays { double db_tx_dly_ns; }; -// Delay the FPGA_CLK by 900ps to ensure a safe ADC_SSCLK -> RADIO_CLK crossing. +// Tune the FPGA->ADC clock delay to ensure a safe ADC_SSCLK -> RADIO_CLK crossing. // If the FPGA_CLK is delayed, we also need to delay the reference clocks going to the DAC // because the data interface clock is generated from FPGA_CLK. -// NOTE: This delay value was verified at room temperature only. static const x300_clk_delays X300_REV0_6_CLK_DELAYS = x300_clk_delays( - /*fpga=*/0.900, /*adc=*/0.000, /*dac=*/0.900, /*db_rx=*/0.000, /*db_tx=*/0.000); + /*fpga=*/0.000, /*adc=*/1.600, /*dac=*/0.000, /*db_rx=*/0.000, /*db_tx=*/0.000); static const x300_clk_delays X300_REV7_CLK_DELAYS = x300_clk_delays( /*fpga=*/0.000, /*adc=*/4.400, /*dac=*/0.000, /*db_rx=*/0.000, /*db_tx=*/0.000); |