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author | Josh Blum <josh@joshknows.com> | 2011-10-13 13:26:07 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2011-11-03 20:37:12 -0700 |
commit | 929571756901c96a984bbb4e415478ac3deb1784 (patch) | |
tree | 8ba48e82d1d27e9df70438a96ff3a3f10f87e65b /host | |
parent | 00b6d8359de6ea616f7bd6573d7f87d635d78a79 (diff) | |
download | uhd-929571756901c96a984bbb4e415478ac3deb1784.tar.gz uhd-929571756901c96a984bbb4e415478ac3deb1784.tar.bz2 uhd-929571756901c96a984bbb4e415478ac3deb1784.zip |
uhd: added converter for item32 as cpu type
Diffstat (limited to 'host')
-rw-r--r-- | host/lib/convert/gen_convert_general.py | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/host/lib/convert/gen_convert_general.py b/host/lib/convert/gen_convert_general.py index be5a65130..eafb145e6 100644 --- a/host/lib/convert/gen_convert_general.py +++ b/host/lib/convert/gen_convert_general.py @@ -28,6 +28,30 @@ TMPL_HEADER = """ using namespace uhd::convert; """ +TMPL_CONV_GEN2_ITEM32 = """ +DECLARE_CONVERTER(item32, 1, sc16_item32_$(end), 1, PRIORITY_GENERAL){ + const item32_t *input = reinterpret_cast<const item32_t *>(inputs[0]); + item32_t *output = reinterpret_cast<item32_t *>(outputs[0]); + + if (scale_factor == 0){} //avoids unused warning + + for (size_t i = 0; i < nsamps; i++){ + output[i] = $(to_wire)(input[i]); + } +} + +DECLARE_CONVERTER(sc16_item32_$(end), 1, item32, 1, PRIORITY_GENERAL){ + const item32_t *input = reinterpret_cast<const item32_t *>(inputs[0]); + item32_t *output = reinterpret_cast<item32_t *>(outputs[0]); + + if (scale_factor == 0){} //avoids unused warning + + for (size_t i = 0; i < nsamps; i++){ + output[i] = $(to_host)(input[i]); + } +} +""" + TMPL_CONV_GEN2_COMPLEX = """ DECLARE_CONVERTER($(cpu_type), 1, sc16_item32_$(end), 1, PRIORITY_GENERAL){ const $(cpu_type)_t *input = reinterpret_cast<const $(cpu_type)_t *>(inputs[0]); @@ -150,6 +174,10 @@ if __name__ == '__main__': TMPL_CONV_GEN2_COMPLEX, end=end, to_host=to_host, to_wire=to_wire, cpu_type=cpu_type ) + output += parse_tmpl( + TMPL_CONV_GEN2_ITEM32, + end=end, to_host=to_host, to_wire=to_wire + ) #generate complex converters for usrp1 format for width in 1, 2, 4: |