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authorWade Fife <wade.fife@ettus.com>2020-08-05 17:37:06 -0500
committerAaron Rossetto <aaron.rossetto@ni.com>2020-08-10 15:18:46 -0500
commitde8b6fcd7137834defbb52242bc4cdec8adb167e (patch)
tree18a97f32ba3892d3d00cf5e14a6c6377225636ba /host/utils
parent2da3cdcb3bd5e00040c7815ec756759be7149414 (diff)
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python: Change default name for rfnoc_image_core
This changes the default name of the image core file to <DEVICE>_rfnoc_image_core.v instead of naming it after the YAML file. This ensures that when you use a custom YAML file, the resulting FPGA build will use the generated rfnoc_image_core and static_router files, rather than just the generated static_router file.
Diffstat (limited to 'host/utils')
-rwxr-xr-xhost/utils/rfnoc_image_builder.py9
1 files changed, 5 insertions, 4 deletions
diff --git a/host/utils/rfnoc_image_builder.py b/host/utils/rfnoc_image_builder.py
index d0c5ae659..9d52fb889 100755
--- a/host/utils/rfnoc_image_builder.py
+++ b/host/utils/rfnoc_image_builder.py
@@ -39,10 +39,10 @@ def setup_parser():
config_group = parser.add_mutually_exclusive_group(required=True)
config_group.add_argument(
- "-y", "--yaml_config",
+ "-y", "--yaml-config",
help="Path to yml configuration file")
config_group.add_argument(
- "-r", "--grc_config",
+ "-r", "--grc-config",
help="Path to grc file to generate config from")
parser.add_argument(
"-F", "--fpga-dir",
@@ -53,11 +53,12 @@ def setup_parser():
parser.add_argument(
"-o", "--image-core-output",
help="Path to where to save the image core Verilog source. "
- "Defaults to the location of the YAML file.")
+ "Defaults to the directory of the YAML file, filename <DEVICE>_rfnoc_image_core.v",
+ default=None)
parser.add_argument(
"-x", "--router-hex-output",
help="Path to where to save the static router hex file. "
- "Defaults to the location of the YAML file, filename $device_static_router.hex",
+ "Defaults to the directory of the YAML file, filename <DEVICE>_static_router.hex",
default=None)
parser.add_argument(
"-I", "--include-dir",