utils: blocktool: Fix blocktool

- Fix mako paths to run from anywhere
- Correct code errors and clean up generated code
- Add support for port parameters
- Add support for axis_data interface
- Fix NoC shell reset handling
- Replace Python functions with Verilog $clog2
- Allow input and output to share port name

25 files changed, 1402 insertions, 585 deletions

diff --git a/host/utils/rfnoc_blocktool/rfnoc_create_verilog.py b/host/utils/rfnoc_blocktool/rfnoc_create_verilog.py
index 7b4f6cdeb..ce8d4cae7 100644
--- a/host/utils/rfnoc_blocktool/rfnoc_create_verilog.py
+++ b/host/utils/rfnoc_blocktool/rfnoc_create_verilog.py
@@ -18,7 +18,6 @@ import os
 import re
 import sys
 from collections import namedtuple
-import six
 import mako.template
 import mako.lookup
 from mako import exceptions
@@ -93,8 +92,11 @@ class BlockGenerator:
         final filename is derived from the template file by substitute template
         by the module name from the YAML configuration.
         """
-        lookup = mako.lookup.TemplateLookup(directories=['.'])
-        filename = os.path.join("templates", self.template_file)
+        # Create absolute paths for templates so run location doesn't matter
+        template_dir = os.path.abspath(os.path.join(os.path.dirname(__file__), 
+                                                    "templates"))
+        lookup = mako.lookup.TemplateLookup(directories=[template_dir])
+        filename = os.path.join(template_dir, self.template_file)
         tpl = mako.template.Template(filename=filename, lookup=lookup,
                                      strict_undefined=True)
         # Render and return
diff --git a/host/utils/rfnoc_blocktool/templates/Makefile b/host/utils/rfnoc_blocktool/templates/Makefile
index ca397bf7d..7b151e3b9 100644
--- a/host/utils/rfnoc_blocktool/templates/Makefile
+++ b/host/utils/rfnoc_blocktool/templates/Makefile
@@ -7,15 +7,20 @@
 #-------------------------------------------------
 # Top-of-Makefile
 #-------------------------------------------------
-# Define BASE_DIR to point to the "top" dir
-BASE_DIR = $(abspath ../../../../top)
+# Define BASE_DIR to point to the "top" dir. Note:
+# UHD_FPGA_DIR must be passed into this Makefile.
+ifndef UHD_FPGA_DIR
+$(error "UHD_FPGA_DIR is not set! Must point to UHD FPGA repository!")
+endif
+BASE_DIR = $(UHD_FPGA_DIR)/usrp3/top
 # Include viv_sim_preample after defining BASE_DIR
 include $(BASE_DIR)/../tools/make/viv_sim_preamble.mak
 
 #-------------------------------------------------
 # Design Specific
 #-------------------------------------------------
-# Include makefiles and sources for the DUT and its dependencies
+# Include makefiles and sources for the DUT and its 
+# dependencies.
 include $(BASE_DIR)/../lib/rfnoc/core/Makefile.srcs
 include $(BASE_DIR)/../lib/rfnoc/utils/Makefile.srcs
 include Makefile.srcs
@@ -23,21 +28,15 @@ include Makefile.srcs
 DESIGN_SRCS += $(abspath ${"\\"}
 $(RFNOC_CORE_SRCS) ${"\\"}
 $(RFNOC_UTIL_SRCS) ${"\\"}
-$(RFNOC_BLOCK_${config['module_name'].upper()}_SRCS) ${"\\"}
+$(RFNOC_OOT_SRCS)  ${"\\"}
 )
 
 #-------------------------------------------------
 # Testbench Specific
 #-------------------------------------------------
-include $(BASE_DIR)/../sim/rfnoc/Makefile.srcs
-
 SIM_TOP = rfnoc_block_${config['module_name']}_tb
-
 SIM_SRCS = ${"\\"}
 $(abspath rfnoc_block_${config['module_name']}_tb.sv) ${"\\"}
-$(SIM_RFNOC_SRCS)
-
-# MODELSIM_USER_DO = $(abspath wave.do)
 
 #-------------------------------------------------
 # Bottom-of-Makefile
diff --git a/host/utils/rfnoc_blocktool/templates/Makefile.srcs b/host/utils/rfnoc_blocktool/templates/Makefile.srcs
index 67fcb1ccc..a434fc6f1 100644
--- a/host/utils/rfnoc_blocktool/templates/Makefile.srcs
+++ b/host/utils/rfnoc_blocktool/templates/Makefile.srcs
@@ -1,13 +1,22 @@
 #
-# Copyright 2018 Ettus Research, A National Instruments Company
+# Copyright 2019 Ettus Research, A National Instruments Brand
 #
 # SPDX-License-Identifier: LGPL-3.0-or-later
 #
 
-${'##################################################'}
-# RFNoC Utility Sources
-${'##################################################'}
-RFNOC_BLOCK_${config['module_name'].upper()}_SRCS = $(abspath $(addprefix $(BASE_DIR)/../lib/rfnoc/blocks/${destination}/, ${"\\"}
+${"##################################################"}
+# RFNoC Block Sources
+${"##################################################"}
+# Here, list all the files that are necessary to synthesize this block. Don't
+# include testbenches!
+# Make sure that the source files are nicely detectable by a regex. Best to put
+# one on each line.
+# The first argument to addprefix is the current path to this Makefile, so the
+# path list is always absolute, regardless of from where we're including or
+# calling this file. RFNOC_OOT_SRCS needs to be a simply expanded variable
+# (not a recursively expanded variable), and we take care of that in the build
+# infrastructure.
+RFNOC_OOT_SRCS += $(addprefix $(dir $(abspath $(lastword $(MAKEFILE_LIST)))), ${"\\"}
 rfnoc_block_${config['module_name']}.v ${"\\"}
 noc_shell_${config['module_name']}.v ${"\\"}
-))
+)
diff --git a/host/utils/rfnoc_blocktool/templates/functions.mako b/host/utils/rfnoc_blocktool/templates/functions.mako
new file mode 100644
index 000000000..b0e4506ec
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/functions.mako
@@ -0,0 +1,31 @@
+<%def name="num_ports_str(direction)">\
+<%
+  # Generate a string for the number of input or output CHDR ports. This takes
+  # into account any parameters that affect the number of ports. The direction 
+  # argument should be the string 'inputs' or 'outputs'.
+  num_ports_cnt = 0
+  num_ports_str = ''
+  for port_name, port_info in config['data'][direction].items():
+    if 'num_ports' in port_info:
+      if str(port_info['num_ports']).isdecimal():
+        num_ports_cnt = num_ports_cnt + int(port_info['num_ports'])
+      else:
+        num_ports_str = num_ports_str + '+' + str(port_info['num_ports'])
+    else:
+      num_ports_cnt = num_ports_cnt + 1
+  num_ports_str = str(num_ports_cnt) + num_ports_str
+%>\
+${num_ports_str}\
+</%def>
+
+<%def name="num_ports_in_str()">\
+## Generate a string for the number of input CHDR ports. This takes into
+## account any parameters that affect the number of ports.
+${num_ports_str('inputs')}\
+</%def>
+
+<%def name="num_ports_out_str()">\
+## Generate a string for the number of output CHDR ports. This takes into
+## account any parameters that affect the number of ports.
+${num_ports_str('outputs')}\
+</%def>
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_connect_template.mako
index ff619b6d9..e866dc210 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_connect_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_connect_template.mako
@@ -1,15 +1,22 @@
-<%page args="num_inputs, num_outputs"/>
-
-%for idx, input in enumerate(config['data']['inputs']):
-  .m_${input}_chdr_tdata(${input}_chdr_tdata),
-  .m_${input}_chdr_tlast(${input}_chdr_tlast),
-  .m_${input}_chdr_tvalid(${input}_chdr_tvalid),
-  .m_${input}_chdr_tready(${input}_chdr_tready)${"," if (idx < num_inputs -1) or (num_outputs > 0) else ""}
+<%
+  # Get the number of input and outputs port names
+  num_inputs  = len(config['data']['inputs'])
+  num_outputs = len(config['data']['outputs'])
+%>\
+    // AXIS-CHDR Clock and Reset
+    .axis_chdr_clk (axis_chdr_clk),
+    .axis_chdr_rst (axis_chdr_rst),
+    // AXIS-CHDR to User Logic
+%for idx, port_name in enumerate(config['data']['inputs']):
+    .m_${port_name}_chdr_tdata  (m_${port_name}_chdr_tdata),
+    .m_${port_name}_chdr_tlast  (m_${port_name}_chdr_tlast),
+    .m_${port_name}_chdr_tvalid (m_${port_name}_chdr_tvalid),
+    .m_${port_name}_chdr_tready (m_${port_name}_chdr_tready)${"," if (idx < num_inputs -1) or (num_outputs > 0) else ""}
 %endfor
-
-%for idx, output in enumerate(config['data']['outputs']):
-  .s_${output}_chdr_tdata(${output}_chdr_tdata),
-  .s_${output}_chdr_tlast(${output}_chdr_tlast),
-  .s_${output}_chdr_tvalid(${output}_chdr_tvalid),
-  .s_${output}_chdr_tready(${output}_chdr_tready)${"," if (idx < num_outputs -1) else ""}
+    // AXIS-CHDR from User Logic
+%for idx, port_name in enumerate(config['data']['outputs']):
+    .s_${port_name}_chdr_tdata  (s_${port_name}_chdr_tdata),
+    .s_${port_name}_chdr_tlast  (s_${port_name}_chdr_tlast),
+    .s_${port_name}_chdr_tvalid (s_${port_name}_chdr_tvalid),
+    .s_${port_name}_chdr_tready (s_${port_name}_chdr_tready)${"," if (idx < num_outputs -1) else ""}
 %endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_modules_template.mako
index bcb23dff6..299d8d7c5 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_modules_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_modules_template.mako
@@ -1,41 +1,114 @@
-%for idx, input in enumerate(config['data']['inputs']):
+  //---------------------
+  // Input Data Paths
+  //---------------------
+
+<%
+  port_index = '0'
+%>\
+%for port_name, port_info in config['data']['inputs'].items():
+<%
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_input_${port_name}
+    chdr_to_chdr_data #(
+      .CHDR_W (CHDR_W)
+    ) chdr_to_chdr_data_in_${port_name} (
+      .axis_chdr_clk      (rfnoc_chdr_clk),
+      .axis_chdr_rst      (rfnoc_chdr_rst),
+      .s_axis_chdr_tdata  (s_rfnoc_chdr_tdata[(${port_index}+i)*CHDR_W+:CHDR_W]),
+      .s_axis_chdr_tlast  (s_rfnoc_chdr_tlast[${port_index}+i]),
+      .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}+i]),
+      .s_axis_chdr_tready (s_rfnoc_chdr_tready[${port_index}+i]),
+      .m_axis_chdr_tdata  (m_${port_name}_chdr_tdata[i*CHDR_W+:CHDR_W]),
+      .m_axis_chdr_tlast  (m_${port_name}_chdr_tlast[i]),
+      .m_axis_chdr_tvalid (m_${port_name}_chdr_tvalid[i]),
+      .m_axis_chdr_tready (m_${port_name}_chdr_tready[i]),
+      .flush_en           (data_i_flush_en),
+      .flush_timeout      (data_i_flush_timeout),
+      .flush_active       (data_i_flush_active[${port_index}+i]),
+      .flush_done         (data_i_flush_done[${port_index}+i])
+    );
+  end
+%else:
   chdr_to_chdr_data #(
-    .CHDR_W(CHDR_W)
-  ) chdr_to_chdr_data_i${idx} (
-    .axis_chdr_clk(rfnoc_chdr_clk),
-    .axis_chdr_rst(rfnoc_chdr_rst),
-    .s_axis_chdr_tdata(s_rfnoc_chdr_tdata[(${idx}*CHDR_W)+:CHDR_W]),
-    .s_axis_chdr_tlast(s_rfnoc_chdr_tlast[${idx}]),  
-    .s_axis_chdr_tvalid(s_rfnoc_chdr_tvalid[${idx}]),
-    .s_axis_chdr_tready(s_rfnoc_chdr_tready[${idx}]),
-    .m_axis_chdr_tdata(m_${input}_chdr_tdata),
-    .m_axis_chdr_tlast(m_${input}_chdr_tlast),
-    .m_axis_chdr_tvalid(m_${input}_chdr_tvalid),
-    .m_axis_chdr_tready(m_${input}_chdr_tready),
-    .flush_en(data_i_flush_en),
-    .flush_timeout(data_i_flush_timeout),
-    .flush_active(data_i_flush_active[${idx}]),
-    .flush_done(data_i_flush_done[${idx}])
+    .CHDR_W (CHDR_W)
+  ) chdr_to_chdr_data_in_${port_name} (
+    .axis_chdr_clk      (rfnoc_chdr_clk),
+    .axis_chdr_rst      (rfnoc_chdr_rst),
+    .s_axis_chdr_tdata  (s_rfnoc_chdr_tdata[(${port_index})*CHDR_W+:CHDR_W]),
+    .s_axis_chdr_tlast  (s_rfnoc_chdr_tlast[${port_index}]),
+    .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}]),
+    .s_axis_chdr_tready (s_rfnoc_chdr_tready[${port_index}]),
+    .m_axis_chdr_tdata  (m_${port_name}_chdr_tdata),
+    .m_axis_chdr_tlast  (m_${port_name}_chdr_tlast),
+    .m_axis_chdr_tvalid (m_${port_name}_chdr_tvalid),
+    .m_axis_chdr_tready (m_${port_name}_chdr_tready),
+    .flush_en           (data_i_flush_en),
+    .flush_timeout      (data_i_flush_timeout),
+    .flush_active       (data_i_flush_active[${port_index}]),
+    .flush_done         (data_i_flush_done[${port_index}])
   );
+%endif
+
+<%
+  port_index = port_index + '+' + str(num_ports) if (port_index != '0') else str(num_ports)
+%>\
 %endfor
+  //---------------------
+  // Output Data Paths
+  //---------------------
 
-%for idx, output in enumerate(config['data']['outputs']):
+<%
+  port_index = '0'
+%>\
+%for port_name, port_info in config['data']['outputs'].items():
+<%
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_output_${port_name}
+    chdr_to_chdr_data #(
+      .CHDR_W (CHDR_W)
+    ) chdr_to_chdr_data_out_${port_name} (
+      .axis_chdr_clk      (rfnoc_chdr_clk),
+      .axis_chdr_rst      (rfnoc_chdr_rst),
+      .m_axis_chdr_tdata  (m_rfnoc_chdr_tdata[(${port_index}+i)*CHDR_W+:CHDR_W]),
+      .m_axis_chdr_tlast  (m_rfnoc_chdr_tlast[${port_index}+i]),
+      .m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[${port_index}+i]),
+      .m_axis_chdr_tready (m_rfnoc_chdr_tready[${port_index}+i]),
+      .s_axis_chdr_tdata  (s_${port_name}_chdr_tdata[i*CHDR_W+:CHDR_W]),
+      .s_axis_chdr_tlast  (s_${port_name}_chdr_tlast[i]),
+      .s_axis_chdr_tvalid (s_${port_name}_chdr_tvalid[i]),
+      .s_axis_chdr_tready (s_${port_name}_chdr_tready[i]),
+      .flush_en           (data_o_flush_en),
+      .flush_timeout      (data_o_flush_timeout),
+      .flush_active       (data_o_flush_active[${port_index}+i]),
+      .flush_done         (data_o_flush_done[${port_index}+i])
+    );
+  end
+%else:
   chdr_to_chdr_data #(
-    .CHDR_W(CHDR_W)
-  ) chdr_to_chdr_data_o${idx} (
-    .axis_chdr_clk(rfnoc_chdr_clk),
-    .axis_chdr_rst(rfnoc_chdr_rst),
-    .m_axis_chdr_tdata(m_rfnoc_chdr_tdata[(${idx}*CHDR_W)+:CHDR_W]),
-    .m_axis_chdr_tlast(m_rfnoc_chdr_tlast[${idx}]),    
-    .m_axis_chdr_tvalid(m_rfnoc_chdr_tvalid[${idx}]),
-    .m_axis_chdr_tready(m_rfnoc_chdr_tready[${idx}]),
-    .s_axis_chdr_tdata(s_${output}_chdr_tdata),
-    .s_axis_chdr_tlast(s_${output}_chdr_tlast),
-    .s_axis_chdr_tvalid(s_${output}_chdr_tvalid),
-    .s_axis_chdr_tready(s_${output}_chdr_tready),
-    .flush_en(data_o_flush_en),
-    .flush_timeout(data_o_flush_timeout),
-    .flush_active(data_o_flush_active[${idx}]),
-    .flush_done(data_o_flush_done[${idx}])
+    .CHDR_W (CHDR_W)
+  ) chdr_to_chdr_data_out_${port_name} (
+    .axis_chdr_clk      (rfnoc_chdr_clk),
+    .axis_chdr_rst      (rfnoc_chdr_rst),
+    .m_axis_chdr_tdata  (m_rfnoc_chdr_tdata[(${port_index})*CHDR_W+:CHDR_W]),
+    .m_axis_chdr_tlast  (m_rfnoc_chdr_tlast[${port_index}]),
+    .m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[${port_index}]),
+    .m_axis_chdr_tready (m_rfnoc_chdr_tready[${port_index}]),
+    .s_axis_chdr_tdata  (s_${port_name}_chdr_tdata),
+    .s_axis_chdr_tlast  (s_${port_name}_chdr_tlast),
+    .s_axis_chdr_tvalid (s_${port_name}_chdr_tvalid),
+    .s_axis_chdr_tready (s_${port_name}_chdr_tready),
+    .flush_en           (data_o_flush_en),
+    .flush_timeout      (data_o_flush_timeout),
+    .flush_active       (data_o_flush_active[${port_index}]),
+    .flush_done         (data_o_flush_done[${port_index}])
   );
-%endfor
+%endif
+
+<%
+  port_index = port_index + '+' + str(num_ports) if (port_index != '0') else str(num_ports)
+%>\
+%endfor
\ No newline at end of file
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_wires_template.mako
index 9453c8fd1..39c1a33f7 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_wires_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_chdr_wires_template.mako
@@ -1,5 +1,4 @@
-<%page args="mode, num_inputs, num_outputs"/>\
-
+<%page args="mode"/>\
 <%
   if mode == "shell":
     sl_pre = "s_"
@@ -8,23 +7,48 @@
     out_wire = "output "
     term = ","
   elif mode == "block":
-    sl_pre = ""
-    ma_pre = ""
+    sl_pre = "s_"
+    ma_pre = "m_"
     in_wire = ""
     out_wire = ""
-    term=";"
+    term = ";"
+  # Get the number of input and outputs port names
+  num_inputs  = len(config['data']['inputs'])
+  num_outputs = len(config['data']['outputs'])
 %>\
 %for idx, port in enumerate(config['data']['inputs']):
-  // Payload Stream to User Logic: ${port}
+<%
+  port_info = config['data']['inputs'][port]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+  // Framework to User Logic: ${port}
+%if num_ports != 1:
+  ${out_wire}wire [${num_ports}*CHDR_W-1:0]  ${ma_pre}${port}_chdr_tdata${term}
+  ${out_wire}wire [${num_ports}-1:0]         ${ma_pre}${port}_chdr_tlast${term}
+  ${out_wire}wire [${num_ports}-1:0]         ${ma_pre}${port}_chdr_tvalid${term}
+  ${in_wire}wire [${num_ports}-1:0]         ${ma_pre}${port}_chdr_tready${term if (term == ";") or (idx < num_inputs -1) or (num_outputs > 0) else ""}
+%else:
   ${out_wire}wire [CHDR_W-1:0]  ${ma_pre}${port}_chdr_tdata${term}
   ${out_wire}wire               ${ma_pre}${port}_chdr_tlast${term}
   ${out_wire}wire               ${ma_pre}${port}_chdr_tvalid${term}
   ${in_wire}wire               ${ma_pre}${port}_chdr_tready${term if (term == ";") or (idx < num_inputs -1) or (num_outputs > 0) else ""}
+%endif
 %endfor
-
 %for idx, port in enumerate(config['data']['outputs']):
+<%
+  port_info = config['data']['outputs'][port]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+  // User Logic to Framework: ${port}
+%if num_ports != 1:
+  ${in_wire}wire [${num_ports}*CHDR_W-1:0]  ${sl_pre}${port}_chdr_tdata${term}
+  ${in_wire}wire [${num_ports}-1:0]         ${sl_pre}${port}_chdr_tlast${term}
+  ${in_wire}wire [${num_ports}-1:0]         ${sl_pre}${port}_chdr_tvalid${term}
+  ${out_wire}wire [${num_ports}-1:0]         ${sl_pre}${port}_chdr_tready${term if (term == ";") or (idx < num_outputs -1) else ""}
+%else:
   ${in_wire}wire [CHDR_W-1:0]  ${sl_pre}${port}_chdr_tdata${term}
   ${in_wire}wire               ${sl_pre}${port}_chdr_tlast${term}
   ${in_wire}wire               ${sl_pre}${port}_chdr_tvalid${term}
   ${out_wire}wire               ${sl_pre}${port}_chdr_tready${term if (term == ";") or (idx < num_outputs -1) else ""}
+%endif
 %endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_connect_template.mako
index cefc97a22..5c36f4a9e 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_connect_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_connect_template.mako
@@ -1,8 +1,13 @@
-  .m_axis_ctrl_tdata(m_axis_ctrl_tdata),
-  .m_axis_ctrl_tlast(m_axis_ctrl_tlast),
-  .m_axis_ctrl_tvalid(m_axis_ctrl_tvalid),
-  .m_axis_ctrl_tready(m_axis_ctrl_tready),
-  .s_axis_ctrl_tdata(s_axis_ctrl_tdata),
-  .s_axis_ctrl_tlast(s_axis_ctrl_tlast),
-  .s_axis_ctrl_tvalid(s_axis_ctrl_tvalid),
-  .s_axis_ctrl_tready(s_axis_ctrl_tready),
+    // AXIS-Ctrl Clock and Reset
+    .axis_ctrl_clk      (axis_ctrl_clk),
+    .axis_ctrl_rst      (axis_ctrl_rst),
+    // AXIS-Ctrl to User Logic
+    .m_axis_ctrl_tdata  (m_axis_ctrl_tdata),
+    .m_axis_ctrl_tlast  (m_axis_ctrl_tlast),
+    .m_axis_ctrl_tvalid (m_axis_ctrl_tvalid),
+    .m_axis_ctrl_tready (m_axis_ctrl_tready),
+    // AXIS-Ctrl from User Logic
+    .s_axis_ctrl_tdata  (s_axis_ctrl_tdata),
+    .s_axis_ctrl_tlast  (s_axis_ctrl_tlast),
+    .s_axis_ctrl_tvalid (s_axis_ctrl_tvalid),
+    .s_axis_ctrl_tready (s_axis_ctrl_tready),
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_modules_template.mako
index 4c349b11b..a491e3973 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_modules_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_modules_template.mako
@@ -1,28 +1,28 @@
 <%!
-import math
-%>
+  import math
+%>\
   axis_ctrl_endpoint #(
-    .SYNC_CLKS(${1 if config['control']['clk_domain'] == "rfnoc_ctrl" else 0}),
-    .SLAVE_FIFO_SIZE(${math.ceil(math.log2(config['control']['fifo_depth']))})         
+    .SYNC_CLKS       (${1 if config['control']['clk_domain'] == "rfnoc_ctrl" else 0}),
+    .SLAVE_FIFO_SIZE ($clog2(${config['control']['fifo_depth']}))
   ) axis_ctrl_endpoint_i (
-    .rfnoc_ctrl_clk(rfnoc_ctrl_clk),
-    .rfnoc_ctrl_rst(rfnoc_ctrl_rst),
-    .axis_ctrl_clk(axis_ctrl_clk),
-    .axis_ctrl_rst(axis_ctrl_rst),
-    .s_rfnoc_ctrl_tdata(s_rfnoc_ctrl_tdata),
-    .s_rfnoc_ctrl_tlast(s_rfnoc_ctrl_tlast),
-    .s_rfnoc_ctrl_tvalid(s_rfnoc_ctrl_tvalid),
-    .s_rfnoc_ctrl_tready(s_rfnoc_ctrl_tready),
-    .m_rfnoc_ctrl_tdata(m_rfnoc_ctrl_tdata),
-    .m_rfnoc_ctrl_tlast(m_rfnoc_ctrl_tlast),
-    .m_rfnoc_ctrl_tvalid(m_rfnoc_ctrl_tvalid),
-    .m_rfnoc_ctrl_tready(m_rfnoc_ctrl_tready),
-    .s_axis_ctrl_tdata(s_axis_ctrl_tdata),
-    .s_axis_ctrl_tlast(s_axis_ctrl_tlast),
-    .s_axis_ctrl_tvalid(s_axis_ctrl_tvalid),
-    .s_axis_ctrl_tready(s_axis_ctrl_tready),
-    .m_axis_ctrl_tdata(m_axis_ctrl_tdata),
-    .m_axis_ctrl_tlast(m_axis_ctrl_tlast),
-    .m_axis_ctrl_tvalid(m_axis_ctrl_tvalid),
-    .m_axis_ctrl_tready(m_axis_ctrl_tready)
-    );
+    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst      (rfnoc_ctrl_rst),
+    .axis_ctrl_clk       (axis_ctrl_clk),
+    .axis_ctrl_rst       (axis_ctrl_rst),
+    .s_rfnoc_ctrl_tdata  (s_rfnoc_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast  (s_rfnoc_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
+    .m_rfnoc_ctrl_tdata  (m_rfnoc_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast  (m_rfnoc_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
+    .s_axis_ctrl_tdata   (s_axis_ctrl_tdata),
+    .s_axis_ctrl_tlast   (s_axis_ctrl_tlast),
+    .s_axis_ctrl_tvalid  (s_axis_ctrl_tvalid),
+    .s_axis_ctrl_tready  (s_axis_ctrl_tready),
+    .m_axis_ctrl_tdata   (m_axis_ctrl_tdata),
+    .m_axis_ctrl_tlast   (m_axis_ctrl_tlast),
+    .m_axis_ctrl_tvalid  (m_axis_ctrl_tvalid),
+    .m_axis_ctrl_tready  (m_axis_ctrl_tready)
+  );
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_wires_template.mako
index dd15bd100..794d71bd8 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_wires_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_ctrl_wires_template.mako
@@ -13,10 +13,12 @@
     out_wire = ""
     term = ";"
 %>\
+  // AXIS-Ctrl to User Logic
   ${out_wire}wire [31:0]        ${ma_pre}axis_ctrl_tdata${term}
   ${out_wire}wire               ${ma_pre}axis_ctrl_tlast${term}
   ${out_wire}wire               ${ma_pre}axis_ctrl_tvalid${term}
   ${in_wire}wire               ${ma_pre}axis_ctrl_tready${term}
+  // AXIS-Ctrl Control from User Logic
   ${in_wire}wire [31:0]        ${sl_pre}axis_ctrl_tdata${term}
   ${in_wire}wire               ${sl_pre}axis_ctrl_tlast${term}
   ${in_wire}wire               ${sl_pre}axis_ctrl_tvalid${term}
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_data_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_data_connect_template.mako
new file mode 100644
index 000000000..2da895702
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_data_connect_template.mako
@@ -0,0 +1,33 @@
+<%
+  # Get the number of input and outputs port names
+  num_inputs  = len(config['data']['inputs'])
+  num_outputs = len(config['data']['outputs'])
+%>\
+    // AXI-Stream Payload Context Clock and Reset
+    .axis_data_clk (axis_data_clk),
+    .axis_data_rst (axis_data_rst),
+%for idx, port_name in enumerate(config['data']['inputs']):
+    // Data Stream to User Logic: ${port_name}
+    .m_${port_name}_axis_tdata      (m_${port_name}_axis_tdata),
+    .m_${port_name}_axis_tkeep      (m_${port_name}_axis_tkeep),
+    .m_${port_name}_axis_tlast      (m_${port_name}_axis_tlast),
+    .m_${port_name}_axis_tvalid     (m_${port_name}_axis_tvalid),
+    .m_${port_name}_axis_tready     (m_${port_name}_axis_tready),
+    .m_${port_name}_axis_ttimestamp (m_${port_name}_axis_ttimestamp),
+    .m_${port_name}_axis_thas_time  (m_${port_name}_axis_thas_time),
+    .m_${port_name}_axis_tlength    (m_${port_name}_axis_tlength),
+    .m_${port_name}_axis_teov       (m_${port_name}_axis_teov),
+    .m_${port_name}_axis_teob       (m_${port_name}_axis_teob)${"," if (idx < num_inputs - 1) or (num_outputs > 0) else ""}
+%endfor
+%for idx, port_name in enumerate(config['data']['outputs']):
+    // Data Stream from User Logic: ${port_name}
+    .s_${port_name}_axis_tdata      (s_${port_name}_axis_tdata),
+    .s_${port_name}_axis_tkeep      (s_${port_name}_axis_tkeep),
+    .s_${port_name}_axis_tlast      (s_${port_name}_axis_tlast),
+    .s_${port_name}_axis_tvalid     (s_${port_name}_axis_tvalid),
+    .s_${port_name}_axis_tready     (s_${port_name}_axis_tready),
+    .s_${port_name}_axis_ttimestamp (s_${port_name}_axis_ttimestamp),
+    .s_${port_name}_axis_thas_time  (s_${port_name}_axis_thas_time),
+    .s_${port_name}_axis_teov       (s_${port_name}_axis_teov),
+    .s_${port_name}_axis_teob       (s_${port_name}_axis_teob)${"," if (idx < num_outputs -1) else ""}
+%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_data_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_data_modules_template.mako
new file mode 100644
index 000000000..f2fa6e9da
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_data_modules_template.mako
@@ -0,0 +1,170 @@
+<%!
+import math
+%>\
+  //---------------------
+  // Input Data Paths
+  //---------------------
+
+<%
+  port_index = '0'
+%>\
+%for port_name, port_info in config['data']['inputs'].items():
+<%
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_input_${port_name}
+    chdr_to_axis_data #(
+      .CHDR_W         (CHDR_W),
+      .ITEM_W         (${port_info['item_width']}),
+      .NIPC           (${port_info['nipc']}),
+      .SYNC_CLKS      (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+      .INFO_FIFO_SIZE ($clog2(${port_info['info_fifo_depth']})),
+      .PYLD_FIFO_SIZE ($clog2(${port_info['payload_fifo_depth']}))
+    ) chdr_to_axis_data_in_${port_name} (
+      .axis_chdr_clk      (rfnoc_chdr_clk),
+      .axis_chdr_rst      (rfnoc_chdr_rst),
+      .axis_data_clk      (axis_data_clk),
+      .axis_data_rst      (axis_data_rst),
+      .s_axis_chdr_tdata  (s_rfnoc_chdr_tdata[((${port_index}+i)*CHDR_W)+:CHDR_W]),
+      .s_axis_chdr_tlast  (s_rfnoc_chdr_tlast[${port_index}+i]),
+      .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}+i]),
+      .s_axis_chdr_tready (s_rfnoc_chdr_tready[${port_index}+i]),
+      .m_axis_tdata       (m_${port_name}_axis_tdata[(${port_info['item_width']}*${port_info['nipc']})*i+:(${port_info['item_width']}*${port_info['nipc']})]),
+      .m_axis_tkeep       (m_${port_name}_axis_tkeep[${port_info['nipc']}*i+:${port_info['nipc']}]),
+      .m_axis_tlast       (m_${port_name}_axis_tlast[i]),
+      .m_axis_tvalid      (m_${port_name}_axis_tvalid[i]),
+      .m_axis_tready      (m_${port_name}_axis_tready[i]),
+      .m_axis_ttimestamp  (m_${port_name}_axis_ttimestamp[64*i+:64]),
+      .m_axis_thas_time   (m_${port_name}_axis_thas_time[i]),
+      .m_axis_tlength     (m_${port_name}_axis_tlength[i*16+:16]),
+      .m_axis_teov        (m_${port_name}_axis_teov[i]),
+      .m_axis_teob        (m_${port_name}_axis_teob[i]),
+      .flush_en           (data_i_flush_en),
+      .flush_timeout      (data_i_flush_timeout),
+      .flush_active       (data_i_flush_active[${port_index}+i]),
+      .flush_done         (data_i_flush_done[${port_index}+i])
+    );
+  end
+%else:
+  chdr_to_axis_data #(
+    .CHDR_W         (CHDR_W),
+    .ITEM_W         (${port_info['item_width']}),
+    .NIPC           (${port_info['nipc']}),
+    .SYNC_CLKS      (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+    .INFO_FIFO_SIZE ($clog2(${port_info['info_fifo_depth']})),
+    .PYLD_FIFO_SIZE ($clog2(${port_info['payload_fifo_depth']}))
+  ) chdr_to_axis_data_in_${port_name} (
+    .axis_chdr_clk      (rfnoc_chdr_clk),
+    .axis_chdr_rst      (rfnoc_chdr_rst),
+    .axis_data_clk      (axis_data_clk),
+    .axis_data_rst      (axis_data_rst),
+    .s_axis_chdr_tdata  (s_rfnoc_chdr_tdata[(${port_index})*CHDR_W+:CHDR_W]),
+    .s_axis_chdr_tlast  (s_rfnoc_chdr_tlast[${port_index}]),
+    .s_axis_chdr_tvalid (s_rfnoc_chdr_tvalid[${port_index}]),
+    .s_axis_chdr_tready (s_rfnoc_chdr_tready[${port_index}]),
+    .m_axis_tdata       (m_${port_name}_axis_tdata),
+    .m_axis_tkeep       (m_${port_name}_axis_tkeep),
+    .m_axis_tlast       (m_${port_name}_axis_tlast),
+    .m_axis_tvalid      (m_${port_name}_axis_tvalid),
+    .m_axis_tready      (m_${port_name}_axis_tready),
+    .m_axis_ttimestamp  (m_${port_name}_axis_ttimestamp),
+    .m_axis_thas_time   (m_${port_name}_axis_thas_time),
+    .m_axis_tlength     (m_${port_name}_axis_tlength),
+    .m_axis_teov        (m_${port_name}_axis_teov),
+    .m_axis_teob        (m_${port_name}_axis_teob),
+    .flush_en           (data_i_flush_en),
+    .flush_timeout      (data_i_flush_timeout),
+    .flush_active       (data_i_flush_active[${port_index}]),
+    .flush_done         (data_i_flush_done[${port_index}])
+  );
+%endif
+
+<%
+  port_index = port_index + '+' + str(num_ports) if (port_index != '0') else str(num_ports)
+%>\
+%endfor
+  //---------------------
+  // Output Data Paths
+  //---------------------
+
+<%
+  port_index = '0'
+%>\
+%for port_name, port_info in config['data']['outputs'].items():
+<%
+  port_info = config['data']['outputs'][port_name]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_output_${port_name}
+    axis_data_to_chdr #(
+      .CHDR_W         (CHDR_W),
+      .ITEM_W         (${port_info['item_width']}),
+      .NIPC           (${port_info['nipc']}),
+      .SYNC_CLKS      (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+      .INFO_FIFO_SIZE ($clog2(${port_info['info_fifo_depth']})),
+      .PYLD_FIFO_SIZE ($clog2(${port_info['payload_fifo_depth']})),
+      .MTU            (MTU)
+    ) axis_data_to_chdr_out_${port_name} (
+      .axis_chdr_clk      (rfnoc_chdr_clk),
+      .axis_chdr_rst      (rfnoc_chdr_rst),
+      .axis_data_clk      (axis_data_clk),
+      .axis_data_rst      (axis_data_rst),
+      .m_axis_chdr_tdata  (m_rfnoc_chdr_tdata[(${port_index}+i)*CHDR_W+:CHDR_W]),
+      .m_axis_chdr_tlast  (m_rfnoc_chdr_tlast[${port_index}+i]),
+      .m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[${port_index}+i]),
+      .m_axis_chdr_tready (m_rfnoc_chdr_tready[${port_index}+i]),
+      .s_axis_tdata       (s_${port_name}_axis_tdata[(${port_info['item_width']}*${port_info['nipc']})*i+:(${port_info['item_width']}*${port_info['nipc']})]),
+      .s_axis_tkeep       (s_${port_name}_axis_tkeep[${port_info['nipc']}*i+:${port_info['nipc']}]),
+      .s_axis_tlast       (s_${port_name}_axis_tlast[i]),
+      .s_axis_tvalid      (s_${port_name}_axis_tvalid[i]),
+      .s_axis_tready      (s_${port_name}_axis_tready[i]),
+      .s_axis_ttimestamp  (s_${port_name}_axis_ttimestamp[64*i+:64]),
+      .s_axis_thas_time   (s_${port_name}_axis_thas_time[i]),
+      .s_axis_teov        (s_${port_name}_axis_teov[i]),
+      .s_axis_teob        (s_${port_name}_axis_teob[i]),
+      .flush_en           (data_o_flush_en),
+      .flush_timeout      (data_o_flush_timeout),
+      .flush_active       (data_o_flush_active[${port_index}+i]),
+      .flush_done         (data_o_flush_done[${port_index}+i])
+    );
+  end
+%else:
+  axis_data_to_chdr #(
+    .CHDR_W         (CHDR_W),
+    .ITEM_W         (${port_info['item_width']}),
+    .NIPC           (${port_info['nipc']}),
+    .SYNC_CLKS      (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+    .INFO_FIFO_SIZE ($clog2(${port_info['info_fifo_depth']})),
+    .PYLD_FIFO_SIZE ($clog2(${port_info['payload_fifo_depth']})),
+    .MTU            (MTU)
+  ) axis_data_to_chdr_out_${port_name} (
+    .axis_chdr_clk      (rfnoc_chdr_clk),
+    .axis_chdr_rst      (rfnoc_chdr_rst),
+    .axis_data_clk      (axis_data_clk),
+    .axis_data_rst      (axis_data_rst),
+    .m_axis_chdr_tdata  (m_rfnoc_chdr_tdata[(${port_index})*CHDR_W+:CHDR_W]),
+    .m_axis_chdr_tlast  (m_rfnoc_chdr_tlast[${port_index}]),
+    .m_axis_chdr_tvalid (m_rfnoc_chdr_tvalid[${port_index}]),
+    .m_axis_chdr_tready (m_rfnoc_chdr_tready[${port_index}]),
+    .s_axis_tdata       (s_${port_name}_axis_tdata),
+    .s_axis_tkeep       (s_${port_name}_axis_tkeep),
+    .s_axis_tlast       (s_${port_name}_axis_tlast),
+    .s_axis_tvalid      (s_${port_name}_axis_tvalid),
+    .s_axis_tready      (s_${port_name}_axis_tready),
+    .s_axis_ttimestamp  (s_${port_name}_axis_ttimestamp),
+    .s_axis_thas_time   (s_${port_name}_axis_thas_time),
+    .s_axis_teov        (s_${port_name}_axis_teov),
+    .s_axis_teob        (s_${port_name}_axis_teob),
+    .flush_en           (data_o_flush_en),
+    .flush_timeout      (data_o_flush_timeout),
+    .flush_active       (data_o_flush_active[${port_index}]),
+    .flush_done         (data_o_flush_done[${port_index}])
+  );
+%endif
+
+<%
+  port_index = port_index + '+' + str(num_ports) if (port_index != '0') else str(num_ports)
+%>\
+%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako
new file mode 100644
index 000000000..4d3c719ae
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_data_wires_template.mako
@@ -0,0 +1,78 @@
+<%page args="mode"/>\
+<%
+  if mode == "shell":
+    sl_pre = "s_"
+    ma_pre = "m_"
+    in_wire = "input  "
+    out_wire = "output "
+    term = ","
+  elif mode == "block":
+    sl_pre = "s_"
+    ma_pre = "m_"
+    in_wire = ""
+    out_wire = ""
+    term = ";"
+  # Get the number of input and outputs port names
+  num_inputs  = len(config['data']['inputs'])
+  num_outputs = len(config['data']['outputs'])
+%>\
+%for idx, port_name in enumerate(config['data']['inputs']):
+<%
+  port_info = config['data']['inputs'][port_name]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  // Data Stream to User Logic: ${port_name}
+  ${out_wire}wire [${num_ports}*${port_info['item_width']}*${port_info['nipc']}-1:0]   ${ma_pre}${port_name}_axis_tdata${term}
+  ${out_wire}wire [${num_ports}*${port_info['nipc']}-1:0]      ${ma_pre}${port_name}_axis_tkeep${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port_name}_axis_tlast${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port_name}_axis_tvalid${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${ma_pre}${port_name}_axis_tready${term}
+  ${out_wire}wire [${num_ports}*CHDR_W-1:0] ${ma_pre}${port_name}_axis_ttimestamp${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port_name}_axis_thas_time${term}
+  ${out_wire}wire [${num_ports}*16-1:0]     ${ma_pre}${port_name}_axis_tlength${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port_name}_axis_teov${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port_name}_axis_teob${term if (term == ";") or (idx < num_inputs - 1) or (num_outputs > 0) else ""}
+%else:
+  // Data Stream to User Logic: ${port_name}
+  ${out_wire}wire [${port_info['item_width']}*${port_info['nipc']}-1:0]    ${ma_pre}${port_name}_axis_tdata${term}
+  ${out_wire}wire [${port_info['nipc']}-1:0]       ${ma_pre}${port_name}_axis_tkeep${term}
+  ${out_wire}wire               ${ma_pre}${port_name}_axis_tlast${term}
+  ${out_wire}wire               ${ma_pre}${port_name}_axis_tvalid${term}
+  ${in_wire}wire               ${ma_pre}${port_name}_axis_tready${term}
+  ${out_wire}wire [CHDR_W-1:0]  ${ma_pre}${port_name}_axis_ttimestamp${term}
+  ${out_wire}wire               ${ma_pre}${port_name}_axis_thas_time${term}
+  ${out_wire}wire [15:0]        ${ma_pre}${port_name}_axis_tlength${term}
+  ${out_wire}wire               ${ma_pre}${port_name}_axis_teov${term}
+  ${out_wire}wire               ${ma_pre}${port_name}_axis_teob${term if (term == ";") or (idx < num_inputs - 1) or (num_outputs > 0) else ""}
+%endif
+%endfor
+%for idx, port_name in enumerate(config['data']['outputs']):
+<%
+  port_info = config['data']['outputs'][port_name]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  // Data Stream to User Logic: ${port_name}
+  ${in_wire}wire [${num_ports}*${port_info['item_width']}*${port_info['nipc']}-1:0]   ${sl_pre}${port_name}_axis_tdata${term}
+  ${in_wire}wire [${num_ports}*${port_info['nipc']}-1:0]      ${sl_pre}${port_name}_axis_tkeep${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port_name}_axis_tlast${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port_name}_axis_tvalid${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${sl_pre}${port_name}_axis_tready${term}
+  ${in_wire}wire [${num_ports}*CHDR_W-1:0] ${sl_pre}${port_name}_axis_ttimestamp${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port_name}_axis_thas_time${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port_name}_axis_teov${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port_name}_axis_teob${term if (term == ";") or (idx < num_inputs - 1) else ""}
+%else:
+  // Data Stream from User Logic: ${port_name}
+  ${in_wire}wire [${port_info['item_width']}*${port_info['nipc']}-1:0]    ${sl_pre}${port_name}_axis_tdata${term}
+  ${in_wire}wire [${port_info['nipc'] - 1}:0]         ${sl_pre}${port_name}_axis_tkeep${term}
+  ${in_wire}wire               ${sl_pre}${port_name}_axis_tlast${term}
+  ${in_wire}wire               ${sl_pre}${port_name}_axis_tvalid${term}
+  ${out_wire}wire               ${sl_pre}${port_name}_axis_tready${term}
+  ${in_wire}wire [CHDR_W-1:0]  ${sl_pre}${port_name}_axis_ttimestamp${term}
+  ${in_wire}wire               ${sl_pre}${port_name}_axis_thas_time${term}
+  ${in_wire}wire               ${sl_pre}${port_name}_axis_teov${term}
+  ${in_wire}wire               ${sl_pre}${port_name}_axis_teob${term if (term == ";") or (idx < num_outputs - 1) else ""}
+%endif
+%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_connect_template.mako
new file mode 100644
index 000000000..e3a6c655b
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_connect_template.mako
@@ -0,0 +1,36 @@
+<%
+  # Get the number of input and outputs port names
+  num_inputs  = len(config['data']['inputs'])
+  num_outputs = len(config['data']['outputs'])
+%>\
+    // AXI-Stream Payload Context Clock and Reset
+    .axis_data_clk (axis_data_clk),
+    .axis_data_rst (axis_data_rst),
+%for idx, port_name in enumerate(config['data']['inputs']):
+    // Payload Stream to User Logic: ${port_name}
+    .m_${port_name}_payload_tdata  (m_${port_name}_payload_tdata),
+    .m_${port_name}_payload_tkeep  (m_${port_name}_payload_tkeep),
+    .m_${port_name}_payload_tlast  (m_${port_name}_payload_tlast),
+    .m_${port_name}_payload_tvalid (m_${port_name}_payload_tvalid),
+    .m_${port_name}_payload_tready (m_${port_name}_payload_tready),
+    // Context Stream to User Logic: ${port_name}
+    .m_${port_name}_context_tdata  (m_${port_name}_context_tdata),
+    .m_${port_name}_context_tuser  (m_${port_name}_context_tuser),
+    .m_${port_name}_context_tlast  (m_${port_name}_context_tlast),
+    .m_${port_name}_context_tvalid (m_${port_name}_context_tvalid),
+    .m_${port_name}_context_tready (m_${port_name}_context_tready)${"," if (idx < num_inputs - 1) or (num_outputs > 0) else ""}
+%endfor
+%for idx, port_name in enumerate(config['data']['outputs']):
+    // Payload Stream from User Logic: ${port_name}
+    .s_${port_name}_payload_tdata  (s_${port_name}_payload_tdata),
+    .s_${port_name}_payload_tkeep  (s_${port_name}_payload_tkeep),
+    .s_${port_name}_payload_tlast  (s_${port_name}_payload_tlast),
+    .s_${port_name}_payload_tvalid (s_${port_name}_payload_tvalid),
+    .s_${port_name}_payload_tready (s_${port_name}_payload_tready),
+    // Context Stream from User Logic: ${port_name}
+    .s_${port_name}_context_tdata  (s_${port_name}_context_tdata),
+    .s_${port_name}_context_tuser  (s_${port_name}_context_tuser),
+    .s_${port_name}_context_tlast  (s_${port_name}_context_tlast),
+    .s_${port_name}_context_tvalid (s_${port_name}_context_tvalid),
+    .s_${port_name}_context_tready (s_${port_name}_context_tready)${"," if (idx < num_outputs -1) else ""}
+%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_modules_template.mako
new file mode 100644
index 000000000..61c8cffd6
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_modules_template.mako
@@ -0,0 +1,178 @@
+<%!
+import math
+%>\
+  //---------------------
+  // Input Data Paths
+  //---------------------
+
+<%
+  port_index = '0'
+%>\
+%for port_name, port_info in config['data']['inputs'].items():
+<%
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_input_${port_name}
+    chdr_to_axis_pyld_ctxt #(
+      .CHDR_W              (CHDR_W),
+      .ITEM_W              (${port_info['item_width']}),
+      .NIPC                (${port_info['nipc']}),
+      .SYNC_CLKS           (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+      .CONTEXT_FIFO_SIZE   ($clog2(${port_info['context_fifo_depth']})),
+      .PAYLOAD_FIFO_SIZE   ($clog2(${port_info['payload_fifo_depth']})),
+      .CONTEXT_PREFETCH_EN (1)
+    ) chdr_to_axis_pyld_ctxt_in_${port_name} (
+      .axis_chdr_clk         (rfnoc_chdr_clk),
+      .axis_chdr_rst         (rfnoc_chdr_rst),
+      .axis_data_clk         (axis_data_clk),
+      .axis_data_rst         (axis_data_rst),
+      .s_axis_chdr_tdata     (s_rfnoc_chdr_tdata[((${port_index}+i)*CHDR_W)+:CHDR_W]),
+      .s_axis_chdr_tlast     (s_rfnoc_chdr_tlast[${port_index}+i]),
+      .s_axis_chdr_tvalid    (s_rfnoc_chdr_tvalid[${port_index}+i]),
+      .s_axis_chdr_tready    (s_rfnoc_chdr_tready[${port_index}+i]),
+      .m_axis_payload_tdata  (m_${port_name}_payload_tdata[(${port_info['item_width']}*${port_info['nipc']})*i+:(${port_info['item_width']}*${port_info['nipc']})]),
+      .m_axis_payload_tkeep  (m_${port_name}_payload_tkeep[${port_info['nipc']}*i+:${port_info['nipc']}]),
+      .m_axis_payload_tlast  (m_${port_name}_payload_tlast[i]),
+      .m_axis_payload_tvalid (m_${port_name}_payload_tvalid[i]),
+      .m_axis_payload_tready (m_${port_name}_payload_tready[i]),
+      .m_axis_context_tdata  (m_${port_name}_context_tdata[CHDR_W*i+:CHDR_W]),
+      .m_axis_context_tuser  (m_${port_name}_context_tuser[4*i+:4]),
+      .m_axis_context_tlast  (m_${port_name}_context_tlast[i]),
+      .m_axis_context_tvalid (m_${port_name}_context_tvalid[i]),
+      .m_axis_context_tready (m_${port_name}_context_tready[i]),
+      .flush_en              (data_i_flush_en),
+      .flush_timeout         (data_i_flush_timeout),
+      .flush_active          (data_i_flush_active[${port_index}+i]),
+      .flush_done            (data_i_flush_done[${port_index}+i])
+    );
+  end
+%else:
+  chdr_to_axis_pyld_ctxt #(
+    .CHDR_W              (CHDR_W),
+    .ITEM_W              (${port_info['item_width']}),
+    .NIPC                (${port_info['nipc']}),
+    .SYNC_CLKS           (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+    .CONTEXT_FIFO_SIZE   ($clog2(${port_info['context_fifo_depth']})),
+    .PAYLOAD_FIFO_SIZE   ($clog2(${port_info['payload_fifo_depth']})),
+    .CONTEXT_PREFETCH_EN (1)
+  ) chdr_to_axis_pyld_ctxt_in_${port_name} (
+    .axis_chdr_clk         (rfnoc_chdr_clk),
+    .axis_chdr_rst         (rfnoc_chdr_rst),
+    .axis_data_clk         (axis_data_clk),
+    .axis_data_rst         (axis_data_rst),
+    .s_axis_chdr_tdata     (s_rfnoc_chdr_tdata[(${port_index})*CHDR_W+:CHDR_W]),
+    .s_axis_chdr_tlast     (s_rfnoc_chdr_tlast[${port_index}]),
+    .s_axis_chdr_tvalid    (s_rfnoc_chdr_tvalid[${port_index}]),
+    .s_axis_chdr_tready    (s_rfnoc_chdr_tready[${port_index}]),
+    .m_axis_payload_tdata  (m_${port_name}_payload_tdata),
+    .m_axis_payload_tkeep  (m_${port_name}_payload_tkeep),
+    .m_axis_payload_tlast  (m_${port_name}_payload_tlast),
+    .m_axis_payload_tvalid (m_${port_name}_payload_tvalid),
+    .m_axis_payload_tready (m_${port_name}_payload_tready),
+    .m_axis_context_tdata  (m_${port_name}_context_tdata),
+    .m_axis_context_tuser  (m_${port_name}_context_tuser),
+    .m_axis_context_tlast  (m_${port_name}_context_tlast),
+    .m_axis_context_tvalid (m_${port_name}_context_tvalid),
+    .m_axis_context_tready (m_${port_name}_context_tready),
+    .flush_en              (data_i_flush_en),
+    .flush_timeout         (data_i_flush_timeout),
+    .flush_active          (data_i_flush_active[${port_index}]),
+    .flush_done            (data_i_flush_done[${port_index}])
+  );
+%endif
+
+<%
+  port_index = port_index + '+' + str(num_ports) if (port_index != '0') else str(num_ports)
+%>\
+%endfor
+  //---------------------
+  // Output Data Paths
+  //---------------------
+
+<%
+  port_index = '0'
+%>\
+%for port_name, port_info in config['data']['outputs'].items():
+<%
+  port_info = config['data']['outputs'][port_name]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  for (i = 0; i < ${num_ports}; i = i + 1) begin: gen_output_${port_name}
+    axis_pyld_ctxt_to_chdr #(
+      .CHDR_W              (CHDR_W),
+      .ITEM_W              (${port_info['item_width']}),
+      .NIPC                (${port_info['nipc']}),
+      .SYNC_CLKS           (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+      .CONTEXT_FIFO_SIZE   ($clog2(${port_info['context_fifo_depth']})),
+      .PAYLOAD_FIFO_SIZE   ($clog2(${port_info['payload_fifo_depth']})),
+      .MTU                 (MTU),
+      .CONTEXT_PREFETCH_EN (1)
+    ) axis_pyld_ctxt_to_chdr_out_${port_name} (
+      .axis_chdr_clk         (rfnoc_chdr_clk),
+      .axis_chdr_rst         (rfnoc_chdr_rst),
+      .axis_data_clk         (axis_data_clk),
+      .axis_data_rst         (axis_data_rst),
+      .m_axis_chdr_tdata     (m_rfnoc_chdr_tdata[(${port_index}+i)*CHDR_W+:CHDR_W]),
+      .m_axis_chdr_tlast     (m_rfnoc_chdr_tlast[${port_index}+i]),
+      .m_axis_chdr_tvalid    (m_rfnoc_chdr_tvalid[${port_index}+i]),
+      .m_axis_chdr_tready    (m_rfnoc_chdr_tready[${port_index}+i]),
+      .s_axis_payload_tdata  (s_${port_name}_payload_tdata[(${port_info['item_width']}*${port_info['nipc']})*i+:(${port_info['item_width']}*${port_info['nipc']})]),
+      .s_axis_payload_tkeep  (s_${port_name}_payload_tkeep[${port_info['nipc']}*i+:${port_info['nipc']}]),
+      .s_axis_payload_tlast  (s_${port_name}_payload_tlast[i]),
+      .s_axis_payload_tvalid (s_${port_name}_payload_tvalid[i]),
+      .s_axis_payload_tready (s_${port_name}_payload_tready[i]),
+      .s_axis_context_tdata  (s_${port_name}_context_tdata[CHDR_W*i+:CHDR_W]),
+      .s_axis_context_tuser  (s_${port_name}_context_tuser[4*i+:4]),
+      .s_axis_context_tlast  (s_${port_name}_context_tlast[i]),
+      .s_axis_context_tvalid (s_${port_name}_context_tvalid[i]),
+      .s_axis_context_tready (s_${port_name}_context_tready[i]),
+      .framer_errors         (),
+      .flush_en              (data_o_flush_en),
+      .flush_timeout         (data_o_flush_timeout),
+      .flush_active          (data_o_flush_active[${port_index}+i]),
+      .flush_done            (data_o_flush_done[${port_index}+i])
+    );
+  end
+%else:
+  axis_pyld_ctxt_to_chdr #(
+    .CHDR_W              (CHDR_W),
+    .ITEM_W              (${port_info['item_width']}),
+    .NIPC                (${port_info['nipc']}),
+    .SYNC_CLKS           (${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),
+    .CONTEXT_FIFO_SIZE   ($clog2(${port_info['context_fifo_depth']})),
+    .PAYLOAD_FIFO_SIZE   ($clog2(${port_info['payload_fifo_depth']})),
+    .MTU                 (MTU),
+    .CONTEXT_PREFETCH_EN (1)
+  ) axis_pyld_ctxt_to_chdr_out_${port_name} (
+    .axis_chdr_clk         (rfnoc_chdr_clk),
+    .axis_chdr_rst         (rfnoc_chdr_rst),
+    .axis_data_clk         (axis_data_clk),
+    .axis_data_rst         (axis_data_rst),
+    .m_axis_chdr_tdata     (m_rfnoc_chdr_tdata[(${port_index})*CHDR_W+:CHDR_W]),
+    .m_axis_chdr_tlast     (m_rfnoc_chdr_tlast[${port_index}]),
+    .m_axis_chdr_tvalid    (m_rfnoc_chdr_tvalid[${port_index}]),
+    .m_axis_chdr_tready    (m_rfnoc_chdr_tready[${port_index}]),
+    .s_axis_payload_tdata  (s_${port_name}_payload_tdata),
+    .s_axis_payload_tkeep  (s_${port_name}_payload_tkeep),
+    .s_axis_payload_tlast  (s_${port_name}_payload_tlast),
+    .s_axis_payload_tvalid (s_${port_name}_payload_tvalid),
+    .s_axis_payload_tready (s_${port_name}_payload_tready),
+    .s_axis_context_tdata  (s_${port_name}_context_tdata),
+    .s_axis_context_tuser  (s_${port_name}_context_tuser),
+    .s_axis_context_tlast  (s_${port_name}_context_tlast),
+    .s_axis_context_tvalid (s_${port_name}_context_tvalid),
+    .s_axis_context_tready (s_${port_name}_context_tready),
+    .framer_errors         (),
+    .flush_en              (data_o_flush_en),
+    .flush_timeout         (data_o_flush_timeout),
+    .flush_active          (data_o_flush_active[${port_index}]),
+    .flush_done            (data_o_flush_done[${port_index}])
+  );
+%endif
+
+<%
+  port_index = port_index + '+' + str(num_ports) if (port_index != '0') else str(num_ports)
+%>\
+%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_wires_template.mako
new file mode 100644
index 000000000..8251749df
--- /dev/null
+++ b/host/utils/rfnoc_blocktool/templates/modules/axis_pyld_ctxt_wires_template.mako
@@ -0,0 +1,84 @@
+<%page args="mode"/>\
+<%
+  if mode == "shell":
+    sl_pre = "s_"
+    ma_pre = "m_"
+    in_wire = "input  "
+    out_wire = "output "
+    term = ","
+  elif mode == "block":
+    sl_pre = "s_"
+    ma_pre = "m_"
+    in_wire = ""
+    out_wire = ""
+    term = ";"
+  # Get the number of input and outputs port names
+  num_inputs  = len(config['data']['inputs'])
+  num_outputs = len(config['data']['outputs'])
+%>\
+%for idx, port in enumerate(config['data']['inputs']):
+<%
+  port_info = config['data']['inputs'][port]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  // Payload Stream to User Logic: ${port}
+  ${out_wire}wire [${num_ports}*${port_info['item_width']}*${port_info['nipc']}-1:0]   ${ma_pre}${port}_payload_tdata${term}
+  ${out_wire}wire [${num_ports}*${port_info['nipc']}-1:0]      ${ma_pre}${port}_payload_tkeep${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port}_payload_tlast${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port}_payload_tvalid${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${ma_pre}${port}_payload_tready${term}
+  // Context Stream to User Logic: ${port}
+  ${out_wire}wire [${num_ports}*CHDR_W-1:0] ${ma_pre}${port}_context_tdata${term}
+  ${out_wire}wire [${num_ports}*4-1:0]      ${ma_pre}${port}_context_tuser${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port}_context_tlast${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${ma_pre}${port}_context_tvalid${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${ma_pre}${port}_context_tready${term if (term == ";") or (idx < num_inputs - 1) or (num_outputs > 0) else ""}
+%else:
+  // Payload Stream to User Logic: ${port}
+  ${out_wire}wire [${port_info['item_width']}*${port_info['nipc']}-1:0]    ${ma_pre}${port}_payload_tdata${term}
+  ${out_wire}wire [${port_info['nipc']}-1:0]       ${ma_pre}${port}_payload_tkeep${term}
+  ${out_wire}wire               ${ma_pre}${port}_payload_tlast${term}
+  ${out_wire}wire               ${ma_pre}${port}_payload_tvalid${term}
+  ${in_wire}wire               ${ma_pre}${port}_payload_tready${term}
+  // Context Stream to User Logic: ${port}
+  ${out_wire}wire [CHDR_W-1:0]  ${ma_pre}${port}_context_tdata${term}
+  ${out_wire}wire [3:0]         ${ma_pre}${port}_context_tuser${term}
+  ${out_wire}wire               ${ma_pre}${port}_context_tlast${term}
+  ${out_wire}wire               ${ma_pre}${port}_context_tvalid${term}
+  ${in_wire}wire               ${ma_pre}${port}_context_tready${term if (term == ";") or (idx < num_inputs - 1) or (num_outputs > 0) else ""}
+%endif
+%endfor
+%for idx, port in enumerate(config['data']['outputs']):
+<%
+  port_info = config['data']['outputs'][port]
+  num_ports = 1 if 'num_ports' not in port_info else port_info['num_ports']
+%>\
+%if num_ports != 1:
+  // Payload Stream to User Logic: ${port}
+  ${in_wire}wire [${num_ports}*${port_info['item_width']}*${port_info['nipc']}-1:0]   ${sl_pre}${port}_payload_tdata${term}
+  ${in_wire}wire [${num_ports}*${port_info['nipc']}-1:0]      ${sl_pre}${port}_payload_tkeep${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port}_payload_tlast${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port}_payload_tvalid${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${sl_pre}${port}_payload_tready${term}
+  // Context Stream to User Logic: ${port}
+  ${in_wire}wire [${num_ports}*CHDR_W-1:0] ${sl_pre}${port}_context_tdata${term}
+  ${in_wire}wire [${num_ports}*4-1:0]      ${sl_pre}${port}_context_tuser${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port}_context_tlast${term}
+  ${in_wire}wire [${num_ports}-1:0]        ${sl_pre}${port}_context_tvalid${term}
+  ${out_wire}wire [${num_ports}-1:0]        ${sl_pre}${port}_context_tready${term if (term == ";") or (idx < num_inputs - 1) else ""}
+%else:
+  // Payload Stream from User Logic: ${port}
+  ${in_wire}wire [${port_info['item_width']}*${port_info['nipc']}-1:0]    ${sl_pre}${port}_payload_tdata${term}
+  ${in_wire}wire [${port_info['nipc'] - 1}:0]         ${sl_pre}${port}_payload_tkeep${term}
+  ${in_wire}wire               ${sl_pre}${port}_payload_tlast${term}
+  ${in_wire}wire               ${sl_pre}${port}_payload_tvalid${term}
+  ${out_wire}wire               ${sl_pre}${port}_payload_tready${term}
+  // Context Stream from User Logic: ${port}
+  ${in_wire}wire [CHDR_W-1:0]  ${sl_pre}${port}_context_tdata${term}
+  ${in_wire}wire [3:0]         ${sl_pre}${port}_context_tuser${term}
+  ${in_wire}wire               ${sl_pre}${port}_context_tlast${term}
+  ${in_wire}wire               ${sl_pre}${port}_context_tvalid${term}
+  ${out_wire}wire               ${sl_pre}${port}_context_tready${term if (term == ";") or (idx < num_outputs - 1) else ""}
+%endif
+%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_raw_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_raw_connect_template.mako
deleted file mode 100644
index c78946289..000000000
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_raw_connect_template.mako
+++ /dev/null
@@ -1,31 +0,0 @@
-<%page args="num_inputs, num_outputs"/>\
-\
-%for idx, input in enumerate(config['data']['inputs']):
-  // Payload Stream to User Logic: ${input}
-  .m_${input}_payload_tdata(${input}_payload_tdata),
-  .m_${input}_payload_tkeep(${input}_payload_tkeep),
-  .m_${input}_payload_tlast(${input}_payload_tlast),
-  .m_${input}_payload_tvalid(${input}_payload_tvalid),
-  .m_${input}_payload_tready(${input}_payload_tready),
-  // Context Stream to User Logic: ${input}
-  .m_${input}_context_tdata(${input}_context_tdata),
-  .m_${input}_context_tuser(${input}_context_tuser),
-  .m_${input}_context_tlast(${input}_context_tlast),
-  .m_${input}_context_tvalid(${input}_context_tvalid),
-  .m_${input}_context_tready(${input}_context_tready)${"," if (idx < num_inputs - 1) or (num_outputs > 0) else ""}
-%endfor
-
-%for idx, output in enumerate(config['data']['outputs']):
-  // Payload Stream from User Logic: ${output}
-  .s_${output}_payload_tdata(${output}_payload_tdata),
-  .s_${output}_payload_tkeep(${output}_payload_tkeep),
-  .s_${output}_payload_tlast(${output}_payload_tlast),
-  .s_${output}_payload_tvalid(${output}_payload_tvalid),
-  .s_${output}_payload_tready(${output}_payload_tready),
-  // Context Stream from User Logic: ${output}
-  .s_${output}_context_tdata(${output}_context_tdata),
-  .s_${output}_context_tuser(${output}_context_tuser),
-  .s_${output}_context_tlast(${output}_context_tlast),
-  .s_${output}_context_tvalid(${output}_context_tvalid),
-  .s_${output}_context_tready(${output}_context_tready)${"," if (idx < num_outputs -1) else ""}
-%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_raw_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_raw_modules_template.mako
deleted file mode 100644
index c181eeedd..000000000
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_raw_modules_template.mako
+++ /dev/null
@@ -1,78 +0,0 @@
-
-%for idx, input in enumerate(config['data']['inputs']):
-  <%
-    port_tmp = config['data']['inputs'][input]
-  %>
-  chdr_to_axis_raw_data #(
-    .CHDR_W(CHDR_W),
-    .ITEM_W(${port_tmp['item_width']}),
-    .NIPC(${port_tmp['nipc']}),
-    .SYNC_CLKS(${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),              
-    .CONTEXT_FIFO_SIZE(${port_tmp['context_fifo_depth']}),      
-    .PAYLOAD_FIFO_SIZE(${port_tmp['payload_fifo_depth']}),      
-    .CONTEXT_PREFETCH_EN(1)     
-  ) chdr_to_axis_raw_data_i${idx} (
-    .axis_chdr_clk(rfnoc_chdr_clk),
-    .axis_chdr_rst(rfnoc_chdr_rst),
-    .axis_data_clk(axis_data_clk),
-    .axis_data_rst(axis_data_rst),
-    .s_axis_chdr_tdata(s_rfnoc_chdr_tdata[(${idx}*CHDR_W)+:CHDR_W]),
-    .s_axis_chdr_tlast(s_rfnoc_chdr_tlast[${idx}]),  
-    .s_axis_chdr_tvalid(s_rfnoc_chdr_tvalid[${idx}]),
-    .s_axis_chdr_tready(s_rfnoc_chdr_tready[${idx}]),
-    .m_axis_payload_tdata(m_${input}_payload_tdata),
-    .m_axis_payload_tkeep(m_${input}_payload_tkeep),
-    .m_axis_payload_tlast(m_${input}_payload_tlast),
-    .m_axis_payload_tvalid(m_${input}_payload_tvalid),
-    .m_axis_payload_tready(m_${input}_payload_tready),
-    .m_axis_context_tdata(m_${input}_context_tdata),
-    .m_axis_context_tuser(m_${input}_context_tuser),
-    .m_axis_context_tlast(m_${input}_context_tlast),
-    .m_axis_context_tvalid(m_${input}_context_tvalid),
-    .m_axis_context_tready(m_${input}_context_tready),
-    .flush_en(data_i_flush_en),
-    .flush_timeout(data_i_flush_timeout),
-    .flush_active(data_i_flush_active[${idx}]), 
-    .flush_done(data_i_flush_done[${idx}])
-  );
-%endfor
-
-%for idx, output in enumerate(config['data']['outputs']):
-  <%
-    port_tmp = config['data']['outputs'][output]
-  %>
-  axis_raw_data_to_chdr #(
-    .CHDR_W(CHDR_W),
-    .ITEM_W(${port_tmp['item_width']}),
-    .NIPC(${port_tmp['nipc']}),
-    .SYNC_CLKS(${1 if config['data']['clk_domain'] == "rfnoc_chdr" else 0}),              
-    .CONTEXT_FIFO_SIZE(${port_tmp['context_fifo_depth']}),      
-    .PAYLOAD_FIFO_SIZE(${port_tmp['payload_fifo_depth']}),      
-    .CONTEXT_PREFETCH_EN(1),    
-    .MTU(MTU)
-  ) axis_raw_data_to_chdr_i${idx} (
-    .axis_chdr_clk(rfnoc_chdr_clk),
-    .axis_chdr_rst(rfnoc_chdr_rst),
-    .axis_data_clk(axis_data_clk),
-    .axis_data_rst(axis_data_rst),
-    .m_axis_chdr_tdata(m_rfnoc_chdr_tdata[(${idx}*CHDR_W)+:CHDR_W]),
-    .m_axis_chdr_tlast(m_rfnoc_chdr_tlast[${idx}]),    
-    .m_axis_chdr_tvalid(m_rfnoc_chdr_tvalid[${idx}]),
-    .m_axis_chdr_tready(m_rfnoc_chdr_tready[${idx}]),
-    .s_axis_payload_tdata(s_${output}_payload_tdata),
-    .s_axis_payload_tkeep(s_${output}_payload_tkeep),
-    .s_axis_payload_tlast(s_${output}_payload_tlast),
-    .s_axis_payload_tvalid(s_${output}_payload_tvalid),
-    .s_axis_payload_tready(s_${output}_payload_tready),
-    .s_axis_context_tdata(s_${output}_context_tdata),
-    .s_axis_context_tuser(s_${output}_context_tuser),
-    .s_axis_context_tlast(s_${output}_context_tlast),
-    .s_axis_context_tvalid(s_${output}_context_tvalid),
-    .s_axis_context_tready(s_${output}_context_tready),
-    .framer_errors(),   
-    .flush_en(data_o_flush_en),
-    .flush_timeout(data_o_flush_timeout),
-    .flush_active(data_o_flush_active[${idx}]),
-    .flush_done(data_o_flush_done[${idx}])
-  );
-%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/axis_raw_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/axis_raw_wires_template.mako
deleted file mode 100644
index abb8ef5e0..000000000
--- a/host/utils/rfnoc_blocktool/templates/modules/axis_raw_wires_template.mako
+++ /dev/null
@@ -1,50 +0,0 @@
-<%page args="mode, num_inputs, num_outputs"/>\
-<%
-  if mode == "shell":
-    sl_pre = "s_"
-    ma_pre = "m_"
-    in_wire = "input  "
-    out_wire = "output "
-    term = ","
-  elif mode == "block":
-    sl_pre = ""
-    ma_pre = ""
-    in_wire = ""
-    out_wire = ""
-    term = ";"
-%>\
-%for idx, port in enumerate(config['data']['inputs']):
-  <%
-    port_tmp = config['data']['inputs'][port]
-  %>\
-  // Payload Stream to User Logic: ${port}
-  ${out_wire}wire [${port_tmp['item_width']*port_tmp['nipc']-1}:0]        ${ma_pre}${port}_payload_tdata${term}
-  ${out_wire}wire [${port_tmp['nipc']-1}:0]         ${ma_pre}${port}_payload_tkeep${term}
-  ${out_wire}wire               ${ma_pre}${port}_payload_tlast${term}
-  ${out_wire}wire               ${ma_pre}${port}_payload_tvalid${term}
-  ${in_wire}wire               ${ma_pre}${port}_payload_tready${term}
-  // Context Stream to User Logic: ${port}
-  ${out_wire}wire [CHDR_W-1:0]  ${ma_pre}${port}_context_tdata${term}
-  ${out_wire}wire [3:0]         ${ma_pre}${port}_context_tuser${term}
-  ${out_wire}wire               ${ma_pre}${port}_context_tlast${term}
-  ${out_wire}wire               ${ma_pre}${port}_context_tvalid${term}
-  ${in_wire}wire               ${ma_pre}${port}_context_tready${term if (term == ";") or (idx < num_inputs - 1) or (num_outputs > 0) else ""}
-%endfor
-
-%for idx, port in enumerate(config['data']['outputs']):
-  <%
-    port_tmp = config['data']['outputs'][port]
-  %>\
-  // Payload Stream from User Logic: ${port}
-  ${in_wire}wire [${port_tmp['item_width'] * port_tmp['nipc'] - 1}:0]        ${sl_pre}${port}_payload_tdata${term}
-  ${in_wire}wire [${port_tmp['nipc'] - 1}:0]         ${sl_pre}${port}_payload_tkeep${term}
-  ${in_wire}wire               ${sl_pre}${port}_payload_tlast${term}
-  ${in_wire}wire               ${sl_pre}${port}_payload_tvalid${term}
-  ${out_wire}wire               ${sl_pre}${port}_payload_tready${term}
-  // Context Stream from User Logic: ${port}
-  ${in_wire}wire [CHDR_W-1:0]  ${sl_pre}${port}_context_tdata${term}
-  ${in_wire}wire [3:0]         ${sl_pre}${port}_context_tuser${term}
-  ${in_wire}wire               ${sl_pre}${port}_context_tlast${term}
-  ${in_wire}wire               ${sl_pre}${port}_context_tvalid${term}
-  ${out_wire}wire               ${sl_pre}${port}_context_tready${term if (term == ";") or (idx < num_outputs -1) else ""}
-%endfor
diff --git a/host/utils/rfnoc_blocktool/templates/modules/ctrlport_connect_template.mako b/host/utils/rfnoc_blocktool/templates/modules/ctrlport_connect_template.mako
index 944f4af16..310f3b53b 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/ctrlport_connect_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/ctrlport_connect_template.mako
@@ -1,41 +1,44 @@
-  // Control Port Master
-  .m_ctrlport_req_wr(m_ctrlport_req_wr),
-  .m_ctrlport_req_rd(m_ctrlport_req_rd),
-  .m_ctrlport_req_addr(m_ctrlport_req_addr),
-  .m_ctrlport_req_data(m_ctrlport_req_data),
+    // CtrlPort Clock and Reset
+    .ctrlport_clk              (ctrlport_clk),
+    .ctrlport_rst              (ctrlport_rst),
+    // CtrlPort Master
+    .m_ctrlport_req_wr         (m_ctrlport_req_wr),
+    .m_ctrlport_req_rd         (m_ctrlport_req_rd),
+    .m_ctrlport_req_addr       (m_ctrlport_req_addr),
+    .m_ctrlport_req_data       (m_ctrlport_req_data),
 %if config['control']['ctrlport']['byte_mode']:
-  .m_ctrlport_req_byte_en(m_ctrlport_req_byte_en),
+    .m_ctrlport_req_byte_en    (m_ctrlport_req_byte_en),
 %endif
 %if config['control']['ctrlport']['timed']:
-  .m_ctrlport_req_has_time(m_ctrlport_req_has_time),
-  .m_ctrlport_req_time(m_ctrlport_req_time),
+    .m_ctrlport_req_has_time   (m_ctrlport_req_has_time),
+    .m_ctrlport_req_time       (m_ctrlport_req_time),
 %endif
-  .m_ctrlport_resp_ack(m_ctrlport_resp_ack),
+    .m_ctrlport_resp_ack       (m_ctrlport_resp_ack),
 %if config['control']['ctrlport']['has_status']:
-  .m_ctrlport_resp_status(m_ctrlport_resp_status),
+    .m_ctrlport_resp_status    (m_ctrlport_resp_status),
 %endif
-  .m_ctrlport_resp_data(m_ctrlport_resp_data),
+    .m_ctrlport_resp_data      (m_ctrlport_resp_data),
 %if config['control']['interface_direction'] != "slave":
-  // Control Port Slave
-  .s_ctrlport_req_wr(s_ctrlport_req_wr),
-  .s_ctrlport_req_rd(s_ctrlport_req_rd),
-  .s_ctrlport_req_addr(s_ctrlport_req_addr),
-  .s_ctrlport_req_portid(s_ctrlport_req_portid),
+    // CtrlPort Slave
+    .s_ctrlport_req_wr         (s_ctrlport_req_wr),
+    .s_ctrlport_req_rd         (s_ctrlport_req_rd),
+    .s_ctrlport_req_addr       (s_ctrlport_req_addr),
+    .s_ctrlport_req_portid     (s_ctrlport_req_portid),
   %if config['control']['interface_direction'] == "remote_master_slave":
-  .s_ctrlport_req_rem_epid(s_ctrlport_req_rem_epid),
-  .s_ctrlport_req_rem_portid(s_ctrlport_req_rem_portid),
+    .s_ctrlport_req_rem_epid   (s_ctrlport_req_rem_epid),
+    .s_ctrlport_req_rem_portid (s_ctrlport_req_rem_portid),
   %endif
-  .s_ctrlport_req_data(s_ctrlport_req_data),
+    .s_ctrlport_req_data       (s_ctrlport_req_data),
   %if config['control']['ctrlport']['byte_mode']:
-  .s_ctrlport_req_byte_en(s_ctrlport_req_byte_en),
+    .s_ctrlport_req_byte_en    (s_ctrlport_req_byte_en),
   %endif
   %if config['control']['ctrlport']['timed']:
-  .s_ctrlport_req_has_time(s_ctrlport_req_has_time),
-  .s_ctrlport_req_time(s_ctrlport_req_time),
+    .s_ctrlport_req_has_time   (s_ctrlport_req_has_time),
+    .s_ctrlport_req_time       (s_ctrlport_req_time),
   %endif
-  .s_ctrlport_resp_ack(s_ctrlport_resp_ack),
+    .s_ctrlport_resp_ack       (s_ctrlport_resp_ack),
   %if config['control']['ctrlport']['has_status']:
-  .s_ctrlport_resp_status(s_ctrlport_resp_status),
+    .s_ctrlport_resp_status    (s_ctrlport_resp_status),
   %endif
-  .s_ctrlport_resp_data(s_ctrlport_resp_data),
+    .s_ctrlport_resp_data      (s_ctrlport_resp_data),
 %endif
diff --git a/host/utils/rfnoc_blocktool/templates/modules/ctrlport_modules_template.mako b/host/utils/rfnoc_blocktool/templates/modules/ctrlport_modules_template.mako
index 9aecc2b80..6dfe7f4be 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/ctrlport_modules_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/ctrlport_modules_template.mako
@@ -1,47 +1,46 @@
 <%!
 import math
-%>
+%>\
   ctrlport_endpoint #(
-    .THIS_PORTID(THIS_PORTID),
-    .SYNC_CLKS(${1 if config['control']['clk_domain'] == "rfnoc_ctrl" else 0}),
-    .AXIS_CTRL_MST_EN(${int(config['control']['interface_direction'] != "slave")}),
-    .AXIS_CTRL_SLV_EN(1),       
-    .SLAVE_FIFO_SIZE(${math.ceil(math.log2(config['control']['fifo_depth']))})         
+    .THIS_PORTID      (THIS_PORTID),
+    .SYNC_CLKS        (${1 if config['control']['clk_domain'] == "rfnoc_ctrl" else 0}),
+    .AXIS_CTRL_MST_EN (${int(config['control']['interface_direction'] != "slave")}),
+    .AXIS_CTRL_SLV_EN (1),
+    .SLAVE_FIFO_SIZE  ($clog2(${config['control']['fifo_depth']}))
   ) ctrlport_endpoint_i (
-    .rfnoc_ctrl_clk(rfnoc_ctrl_clk),
-    .rfnoc_ctrl_rst(rfnoc_ctrl_rst),
-    .ctrlport_clk(ctrlport_clk),
-    .ctrlport_rst(ctrlport_rst),
-    .s_rfnoc_ctrl_tdata(s_rfnoc_ctrl_tdata),
-    .s_rfnoc_ctrl_tlast(s_rfnoc_ctrl_tlast),
-    .s_rfnoc_ctrl_tvalid(s_rfnoc_ctrl_tvalid),
-    .s_rfnoc_ctrl_tready(s_rfnoc_ctrl_tready),
-    .m_rfnoc_ctrl_tdata(m_rfnoc_ctrl_tdata),
-    .m_rfnoc_ctrl_tlast(m_rfnoc_ctrl_tlast),
-    .m_rfnoc_ctrl_tvalid(m_rfnoc_ctrl_tvalid),
-    .m_rfnoc_ctrl_tready(m_rfnoc_ctrl_tready),
-    .m_ctrlport_req_wr(m_ctrlport_req_wr),
-    .m_ctrlport_req_rd(m_ctrlport_req_rd),
-    .m_ctrlport_req_addr(m_ctrlport_req_addr),
-    .m_ctrlport_req_data(m_ctrlport_req_data),
-    .m_ctrlport_req_byte_en(${"m_ctrlport_req_byte_en" if config['control']['ctrlport']['byte_mode'] else ""}),        
-    .m_ctrlport_req_has_time(${"m_ctrlport_req_has_time" if config['control']['ctrlport']['timed'] else ""}),      
-    .m_ctrlport_req_time(${"m_ctrlport_req_time" if config['control']['ctrlport']['timed'] else ""}),              
-    .m_ctrlport_resp_ack(m_ctrlport_resp_ack),
-    .m_ctrlport_resp_status(${"m_ctrlport_resp_status" if config['control']['ctrlport']['has_status'] else "'h0"}),        
-    .m_ctrlport_resp_data(m_ctrlport_resp_data),
-    .s_ctrlport_req_wr(${"s_ctrlport_req_wr" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_rd(${"s_ctrlport_req_rd" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_addr(${"s_ctrlport_req_addr" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_portid(${"s_ctrlport_req_portid" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_rem_epid(${"s_ctrlport_req_rem_epid" if config['control']['interface_direction'] == "remote_master_slave" else "'h0"}),
-    .s_ctrlport_req_rem_portid(${"s_ctrlport_req_rem_portid" if config['control']['interface_direction'] == "remote_master_slave" else "'h0"}),
-    .s_ctrlport_req_data(${"s_ctrlport_req_data" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_byte_en(${"s_ctrlport_req_byte_en" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_has_time(${"s_ctrlport_req_has_time" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_req_time(${"s_ctrlport_req_time" if config['control']['interface_direction'] != "slave" else "'h0"}),
-    .s_ctrlport_resp_ack(${"s_ctrlport_resp_ack" if config['control']['interface_direction'] != "slave" else ""}),
-    .s_ctrlport_resp_status(${"s_ctrlport_resp_status" if config['control']['interface_direction'] != "slave" else ""}),
-    .s_ctrlport_resp_data(${"s_ctrlport_resp_data" if config['control']['interface_direction'] != "slave" else ""})
-    );
-  
\ No newline at end of file
+    .rfnoc_ctrl_clk            (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst            (rfnoc_ctrl_rst),
+    .ctrlport_clk              (ctrlport_clk),
+    .ctrlport_rst              (ctrlport_rst),
+    .s_rfnoc_ctrl_tdata        (s_rfnoc_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast        (s_rfnoc_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid       (s_rfnoc_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready       (s_rfnoc_ctrl_tready),
+    .m_rfnoc_ctrl_tdata        (m_rfnoc_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast        (m_rfnoc_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid       (m_rfnoc_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready       (m_rfnoc_ctrl_tready),
+    .m_ctrlport_req_wr         (m_ctrlport_req_wr),
+    .m_ctrlport_req_rd         (m_ctrlport_req_rd),
+    .m_ctrlport_req_addr       (m_ctrlport_req_addr),
+    .m_ctrlport_req_data       (m_ctrlport_req_data),
+    .m_ctrlport_req_byte_en    (${"m_ctrlport_req_byte_en" if config['control']['ctrlport']['byte_mode'] else ""}),
+    .m_ctrlport_req_has_time   (${"m_ctrlport_req_has_time" if config['control']['ctrlport']['timed'] else ""}),
+    .m_ctrlport_req_time       (${"m_ctrlport_req_time" if config['control']['ctrlport']['timed'] else ""}),
+    .m_ctrlport_resp_ack       (m_ctrlport_resp_ack),
+    .m_ctrlport_resp_status    (${"m_ctrlport_resp_status" if config['control']['ctrlport']['has_status'] else "2'b0"}),
+    .m_ctrlport_resp_data      (m_ctrlport_resp_data),
+    .s_ctrlport_req_wr         (${"s_ctrlport_req_wr" if config['control']['interface_direction'] != "slave" else "1'b0"}),
+    .s_ctrlport_req_rd         (${"s_ctrlport_req_rd" if config['control']['interface_direction'] != "slave" else "1'b0"}),
+    .s_ctrlport_req_addr       (${"s_ctrlport_req_addr" if config['control']['interface_direction'] != "slave" else "20'b0"}),
+    .s_ctrlport_req_portid     (${"s_ctrlport_req_portid" if config['control']['interface_direction'] != "slave" else "10'b0"}),
+    .s_ctrlport_req_rem_epid   (${"s_ctrlport_req_rem_epid" if config['control']['interface_direction'] == "remote_master_slave" else "16'b0"}),
+    .s_ctrlport_req_rem_portid (${"s_ctrlport_req_rem_portid" if config['control']['interface_direction'] == "remote_master_slave" else "10'b0"}),
+    .s_ctrlport_req_data       (${"s_ctrlport_req_data" if config['control']['interface_direction'] != "slave" else "32'b0"}),
+    .s_ctrlport_req_byte_en    (${"s_ctrlport_req_byte_en" if config['control']['interface_direction'] != "slave" and config['control']['ctrlport']['byte_mode'] else "4'hF"}),
+    .s_ctrlport_req_has_time   (${"s_ctrlport_req_has_time" if config['control']['interface_direction'] != "slave" and config['control']['ctrlport']['timed'] else "1'b0"}),
+    .s_ctrlport_req_time       (${"s_ctrlport_req_time" if config['control']['interface_direction'] != "slave"  and config['control']['ctrlport']['timed'] else "64'b0"}),
+    .s_ctrlport_resp_ack       (${"s_ctrlport_resp_ack" if config['control']['interface_direction'] != "slave" else ""}),
+    .s_ctrlport_resp_status    (${"s_ctrlport_resp_status" if config['control']['interface_direction'] != "slave" and config['control']['ctrlport']['has_status'] else ""}),
+    .s_ctrlport_resp_data      (${"s_ctrlport_resp_data" if config['control']['interface_direction'] != "slave" else ""})
+  );
diff --git a/host/utils/rfnoc_blocktool/templates/modules/ctrlport_wires_template.mako b/host/utils/rfnoc_blocktool/templates/modules/ctrlport_wires_template.mako
index 6d149ae6b..8d989677a 100644
--- a/host/utils/rfnoc_blocktool/templates/modules/ctrlport_wires_template.mako
+++ b/host/utils/rfnoc_blocktool/templates/modules/ctrlport_wires_template.mako
@@ -14,7 +14,7 @@
     ma_wire = ""
     term = ";"
 %>\
-  // Control Port Master
+  // CtrlPort Master
   ${ma_wire}wire               ${ma_pre}ctrlport_req_wr${term}
   ${ma_wire}wire               ${ma_pre}ctrlport_req_rd${term}
   ${ma_wire}wire [19:0]        ${ma_pre}ctrlport_req_addr${term}
@@ -23,7 +23,7 @@
   ${ma_wire}wire [3:0]         ${ma_pre}ctrlport_req_byte_en${term}
 %endif
 %if config['control']['ctrlport']['timed']:
-  ${ma_wire}wire               ${ma_pre}ctrlport_req_ha${sl_pre}time${term}
+  ${ma_wire}wire               ${ma_pre}ctrlport_req_has_time${term}
   ${ma_wire}wire [63:0]        ${ma_pre}ctrlport_req_time${term}
 %endif
   ${sl_wire}wire               ${ma_pre}ctrlport_resp_ack${term}
@@ -31,9 +31,8 @@
   ${sl_wire}wire [1:0]         ${ma_pre}ctrlport_resp_status${term}
 %endif
   ${sl_wire}wire [31:0]        ${ma_pre}ctrlport_resp_data${term}
-
 %if config['control']['interface_direction'] != "slave":
-  // Control Port Slave
+  // CtrlPort Slave
   ${sl_wire}wire               ${sl_pre}ctrlport_req_wr${term}
   ${sl_wire}wire               ${sl_pre}ctrlport_req_rd${term}
   ${sl_wire}wire [19:0]        ${sl_pre}ctrlport_req_addr${term}
diff --git a/host/utils/rfnoc_blocktool/templates/noc_shell_template.v.mako b/host/utils/rfnoc_blocktool/templates/noc_shell_template.v.mako
index 7fb1b17d5..ec7fdec87 100644
--- a/host/utils/rfnoc_blocktool/templates/noc_shell_template.v.mako
+++ b/host/utils/rfnoc_blocktool/templates/noc_shell_template.v.mako
@@ -1,88 +1,119 @@
 <%!
 import math
-%>
+%>\
+<%namespace name="func" file="/functions.mako"/>\
 //
 // Copyright 2019 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 // Module: noc_shell_${config['module_name']}
-// Description:
+//
+// Description: 
+//
+//   This is a tool-generated NoC-shell for the ${config['module_name']} block.
+//   See the RFNoC specification for more information about NoC shells.
 //
 // Parameters:
 //
-// Signals:
+//   THIS_PORTID : Control crossbar port to which this block is connected
+//   CHDR_W      : AXIS-CHDR data bus width
+//   MTU         : Maximum transmission unit (i.e., maximum packet size in
+//
+
+`default_nettype none
+
 
 module noc_shell_${config['module_name']} #(
-  parameter CHDR_W = 64,
-  parameter [9:0] THIS_PORTID = 10'd0,
-  parameter [5:0] MTU = 0
-)(
+  parameter [9:0] THIS_PORTID     = 10'd0,
+  parameter       CHDR_W          = 64,
+  parameter [5:0] MTU             = 10${"," if ('parameters' in config) else ""}
+%if 'parameters' in config:
+<% param_count = 1 %>\
+%for param, value in config['parameters'].items():
+  parameter       ${'{:<15}'.format(param)} = ${value}${',' if param_count < len(config['parameters']) else ''}
+<% param_count = param_count+1 %>\
+% endfor
+%endif
+) (
+  //---------------------
   // Framework Interface
-  //------------------------------------------------------------
-  // RFNoC Framework Clocks and Resets
+  //---------------------
+
+  // RFNoC Framework Clocks
 %for clock in config['clocks']:
   input  wire ${clock['name']}_clk,
-  ${"output" if clock['name'] in ["rfnoc_chdr", "rfnoc_ctrl"] else "input"} wire ${clock['name']}_rst,
+% endfor
+
+  // NoC Shell Generated Resets
+%for clock in config['clocks']:
+  output wire ${clock['name']}_rst,
 % endfor
 
   // RFNoC Backend Interface
   input  wire [511:0]          rfnoc_core_config,
   output wire [511:0]          rfnoc_core_status,
-  <%
-  num_inputs = len(config['data']['inputs'])
-  num_outputs = len(config['data']['outputs'])
-  %>
-  // CHDR Input Ports (from framework)
-  input  wire [(${num_inputs}*CHDR_W)-1:0] s_rfnoc_chdr_tdata,
-  input  wire [${num_inputs-1}:0]            s_rfnoc_chdr_tlast,
-  input  wire [${num_inputs-1}:0]            s_rfnoc_chdr_tvalid,
-  output wire [${num_inputs-1}:0]            s_rfnoc_chdr_tready,
-
-  // CHDR Output Ports (to framework)
-  output wire [(${num_outputs}*CHDR_W)-1:0] m_rfnoc_chdr_tdata,
-  output wire [${num_outputs-1}:0]            m_rfnoc_chdr_tlast,
-  output wire [${num_outputs-1}:0]            m_rfnoc_chdr_tvalid,
-  input  wire [${num_outputs-1}:0]            m_rfnoc_chdr_tready,
-  // AXIS-Ctrl Input Port (from framework)
+
+  // AXIS-CHDR Input Ports (from framework)
+  input  wire [(${func.num_ports_in_str()})*CHDR_W-1:0] s_rfnoc_chdr_tdata,
+  input  wire [(${func.num_ports_in_str()})-1:0]        s_rfnoc_chdr_tlast,
+  input  wire [(${func.num_ports_in_str()})-1:0]        s_rfnoc_chdr_tvalid,
+  output wire [(${func.num_ports_in_str()})-1:0]        s_rfnoc_chdr_tready,
+  // AXIS-CHDR Output Ports (to framework)
+  output wire [(${func.num_ports_out_str()})*CHDR_W-1:0] m_rfnoc_chdr_tdata,
+  output wire [(${func.num_ports_out_str()})-1:0]        m_rfnoc_chdr_tlast,
+  output wire [(${func.num_ports_out_str()})-1:0]        m_rfnoc_chdr_tvalid,
+  input  wire [(${func.num_ports_out_str()})-1:0]        m_rfnoc_chdr_tready,
+
+  // AXIS-Ctrl Control Input Port (from framework)
   input  wire [31:0]           s_rfnoc_ctrl_tdata,
   input  wire                  s_rfnoc_ctrl_tlast,
   input  wire                  s_rfnoc_ctrl_tvalid,
   output wire                  s_rfnoc_ctrl_tready,
-  // AXIS-Ctrl Output Port (to framework)
+  // AXIS-Ctrl Control Output Port (to framework)
   output wire [31:0]           m_rfnoc_ctrl_tdata,
   output wire                  m_rfnoc_ctrl_tlast,
   output wire                  m_rfnoc_ctrl_tvalid,
   input  wire                  m_rfnoc_ctrl_tready,
 
+  //---------------------
   // Client Interface
-  //------------------------------------------------------------
-  output wire               ctrlport_clk,
-  output wire               ctrlport_rst,
+  //---------------------
 
 %if config['control']['fpga_iface'] == "ctrlport":
-<%include file="modules/ctrlport_wires_template.mako" args="mode='shell'"/>
+  // CtrlPort Clock and Reset
+  output wire               ctrlport_clk,
+  output wire               ctrlport_rst,
+<%include file="/modules/ctrlport_wires_template.mako" args="mode='shell'"/>\
 %elif config['control']['fpga_iface'] == "axis_ctrl":
-<%include file="modules/axis_ctrl_wires_template.mako" args="mode='shell'"/>
-%else:
-<%include file="control wires template.mako"/>
+  // AXIS-Ctrl Clock and Reset
+  output wire               axis_ctrl_clk,
+  output wire               axis_ctrl_rst,
+<%include file="/modules/axis_ctrl_wires_template.mako" args="mode='shell'"/>\
 %endif
 
+%if config['data']['fpga_iface'] == "axis_chdr":
+  // AXIS-CHDR Clock and Reset
+  output wire               axis_chdr_clk,
+  output wire               axis_chdr_rst,
+<%include file="/modules/axis_chdr_wires_template.mako" args="mode='shell'"/>\
+%elif config['data']['fpga_iface'] == "axis_pyld_ctxt":
+  // AXI-Stream Payload Context Clock and Reset
   output wire               axis_data_clk,
   output wire               axis_data_rst,
-
-%if config['data']['fpga_iface'] == "axis_chdr":
-  <%include file="modules/axis_chdr_wires_template.mako" args="mode='shell', num_inputs=num_inputs, num_outputs=num_outputs"/>
-%elif config['data']['fpga_iface'] == "axis_rawdata":
-  <%include file="modules/axis_raw_wires_template.mako" args="mode='shell', num_inputs=num_inputs, num_outputs=num_outputs"/>
-%else:
-  <%include file="data wires template.mako"/>
+<%include file="/modules/axis_pyld_ctxt_wires_template.mako" args="mode='shell'"/>\
+%elif config['data']['fpga_iface'] == "axis_data":
+  // AXI-Stream Data Clock and Reset
+  output wire               axis_data_clk,
+  output wire               axis_data_rst,
+<%include file="/modules/axis_data_wires_template.mako" args="mode='shell'"/>\
 %endif
 );
 
-  // ---------------------------------------------------
+  //---------------------------------------------------------------------------
   //  Backend Interface
-  // ---------------------------------------------------
+  //---------------------------------------------------------------------------
+
   wire         data_i_flush_en;
   wire [31:0]  data_i_flush_timeout;
   wire [63:0]  data_i_flush_active;
@@ -92,56 +123,91 @@ module noc_shell_${config['module_name']} #(
   wire [63:0]  data_o_flush_active;
   wire [63:0]  data_o_flush_done;
 
-
   backend_iface #(
-    .NOC_ID(32'h${format(config['noc_id'], "08X")}),
-    .NUM_DATA_I(${num_inputs}),
-    .NUM_DATA_O(${num_outputs}),
-    .CTRL_FIFOSIZE(${math.ceil(math.log2(config['control']['fifo_depth']))}),
-    .MTU(MTU)
+    .NOC_ID        (32'h${format(config['noc_id'], "08X")}),
+    .NUM_DATA_I    (${func.num_ports_in_str()}),
+    .NUM_DATA_O    (${func.num_ports_out_str()}),
+    .CTRL_FIFOSIZE ($clog2(${config['control']['fifo_depth']})),
+    .MTU           (MTU)
   ) backend_iface_i (
-    .rfnoc_chdr_clk(rfnoc_chdr_clk),
-    .rfnoc_chdr_rst(rfnoc_chdr_rst),
-    .rfnoc_ctrl_clk(rfnoc_ctrl_clk),
-    .rfnoc_ctrl_rst(rfnoc_ctrl_rst),
-    .rfnoc_core_config(rfnoc_core_config),
-    .rfnoc_core_status(rfnoc_core_status),
-    .data_i_flush_en(data_i_flush_en),
-    .data_i_flush_timeout(data_i_flush_timeout),
-    .data_i_flush_active(data_i_flush_active),
-    .data_i_flush_done(data_i_flush_done),
-    .data_o_flush_en(data_o_flush_en),
-    .data_o_flush_timeout(data_o_flush_timeout),
-    .data_o_flush_active(data_o_flush_active),
-    .data_o_flush_done(data_o_flush_done)
+    .rfnoc_chdr_clk       (rfnoc_chdr_clk),
+    .rfnoc_chdr_rst       (rfnoc_chdr_rst),
+    .rfnoc_ctrl_clk       (rfnoc_ctrl_clk),
+    .rfnoc_ctrl_rst       (rfnoc_ctrl_rst),
+    .rfnoc_core_config    (rfnoc_core_config),
+    .rfnoc_core_status    (rfnoc_core_status),
+    .data_i_flush_en      (data_i_flush_en),
+    .data_i_flush_timeout (data_i_flush_timeout),
+    .data_i_flush_active  (data_i_flush_active),
+    .data_i_flush_done    (data_i_flush_done),
+    .data_o_flush_en      (data_o_flush_en),
+    .data_o_flush_timeout (data_o_flush_timeout),
+    .data_o_flush_active  (data_o_flush_active),
+    .data_o_flush_done    (data_o_flush_done)
+  );
+
+<% reset_comment_block = False %>\
+%for clock in config['clocks']:
+  %if clock['name'] not in ["rfnoc_chdr", "rfnoc_ctrl"]:
+    %if not reset_comment_block:
+  //---------------------------------------------------------------------------
+  //  Reset Generation
+  //---------------------------------------------------------------------------
+<% reset_comment_block = True %>
+%endif
+  wire ${clock['name']}_rst_pulse;
+
+  pulse_synchronizer #(.MODE ("POSEDGE")) pulse_synchronizer_${clock['name']} (
+    .clk_a(rfnoc_chdr_clk), .rst_a(1'b0), .pulse_a (rfnoc_chdr_rst), .busy_a (),
+    .clk_b(${clock['name']}_clk), .pulse_b (${clock['name']}_rst_pulse)
   );
 
-  // ---------------------------------------------------
+  pulse_stretch_min #(.LENGTH(32)) pulse_stretch_min_${clock['name']} (
+    .clk(rfnoc_ctrl_clk), .rst(1'b0),
+    .pulse_in(${clock['name']}_rst_pulse), .pulse_out(${clock['name']}_rst)
+  );
+
+%endif
+%endfor
+  //---------------------------------------------------------------------------
   //  Control Path
-  // ---------------------------------------------------
+  //---------------------------------------------------------------------------
+
+%if config['control']['fpga_iface'] == "axis_ctrl":
+  assign axis_ctrl_clk = ${config['control']['clk_domain']}_clk;
+  assign axis_ctrl_rst = ${config['control']['clk_domain']}_rst;
 
+<%include file="/modules/axis_ctrl_modules_template.mako"/>\
+%elif config['control']['fpga_iface'] == "ctrlport":
   assign ctrlport_clk = ${config['control']['clk_domain']}_clk;
   assign ctrlport_rst = ${config['control']['clk_domain']}_rst;
 
-%if config['control']['fpga_iface'] == "axis_ctrl":
-<%include file="modules/axis_ctrl_modules_template.mako"/>
-%elif config['control']['fpga_iface'] == "ctrlport":
-<%include file="modules/ctrlport_modules_template.mako"/>
-%else:
-<%include file="control module template.mako"/>
+<%include file="/modules/ctrlport_modules_template.mako"/>\
 %endif
 
-  // ---------------------------------------------------
+  //---------------------------------------------------------------------------
   //  Data Path
-  // ---------------------------------------------------
+  //---------------------------------------------------------------------------
+
+  genvar i;
+
+%if config['data']['fpga_iface'] == "axis_pyld_ctxt":
   assign axis_data_clk = ${config['data']['clk_domain']}_clk;
   assign axis_data_rst = ${config['data']['clk_domain']}_rst;
-%if config['data']['fpga_iface'] == "axis_rawdata":
-<%include file="modules/axis_raw_modules_template.mako"/>
+
+<%include file="/modules/axis_pyld_ctxt_modules_template.mako"/>\
 %elif config['data']['fpga_iface'] == "axis_chdr":
-<%include file="modules/axis_chdr_modules_template.mako"/>
-%else:
-<%include file="data module template.mako"/>
+  assign axis_chdr_clk = ${config['data']['clk_domain']}_clk;
+  assign axis_chdr_rst = ${config['data']['clk_domain']}_rst;
+  
+<%include file="/modules/axis_chdr_modules_template.mako"/>\
+%elif config['data']['fpga_iface'] == "axis_data":
+  assign axis_data_clk = ${config['data']['clk_domain']}_clk;
+  assign axis_data_rst = ${config['data']['clk_domain']}_rst;
+  
+<%include file="/modules/axis_data_modules_template.mako"/>\
 %endif
-
 endmodule // noc_shell_${config['module_name']}
+
+
+`default_nettype wire
diff --git a/host/utils/rfnoc_blocktool/templates/rfnoc_block_template.v.mako b/host/utils/rfnoc_blocktool/templates/rfnoc_block_template.v.mako
index a2e03ea92..b056a2893 100644
--- a/host/utils/rfnoc_blocktool/templates/rfnoc_block_template.v.mako
+++ b/host/utils/rfnoc_blocktool/templates/rfnoc_block_template.v.mako
@@ -1,48 +1,58 @@
 <%!
 import math
-%>
+%>\
+<%namespace name="func" file="/functions.mako"/>\
 //
 // Copyright 2019 Ettus Research, A National Instruments Brand
 //
 // SPDX-License-Identifier: LGPL-3.0-or-later
 //
 // Module: rfnoc_block_${config['module_name']}
+//
 // Description:
 //
+//   <Add block description here>
+//
 // Parameters:
 //
-// Signals:
+//   THIS_PORTID : Control crossbar port to which this block is connected
+//   CHDR_W      : AXIS-CHDR data bus width
+//   MTU         : Maximum transmission unit (i.e., maximum packet size in
+//                 CHDR words is 2**MTU).
+//
+
+`default_nettype none
 
-<%
-num_inputs = len(config['data']['inputs'])
-num_outputs = len(config['data']['outputs'])
-%>
 
 module rfnoc_block_${config['module_name']} #(
-  parameter  [9:0] THIS_PORTID = 10'd0,
-  parameter        CHDR_W      = 64,
-  parameter  [5:0] MTU         = ${math.ceil(math.log2(config['data']['mtu']))}
+  parameter [9:0] THIS_PORTID     = 10'd0,
+  parameter       CHDR_W          = 64,
+  parameter [5:0] MTU             = 10${"," if ('parameters' in config) else ""}
+%if 'parameters' in config:
+<% param_count = 1 %>\
+%for param, value in config['parameters'].items():
+  parameter       ${'{:<15}'.format(param)} = ${value}${',' if param_count < len(config['parameters']) else ''}
+<% param_count = param_count+1 %>\
+% endfor
+%endif
 )(
   // RFNoC Framework Clocks and Resets
 %for clock in config['clocks']:
   input  wire                   ${clock['name']}_clk,
-  %if not clock['name'] in ["rfnoc_chdr", "rfnoc_ctrl"]:
-  input  wire                   ${clock['name']}_rst,
-  %endif
 %endfor
   // RFNoC Backend Interface
   input  wire [511:0]           rfnoc_core_config,
   output wire [511:0]           rfnoc_core_status,
-  // 2 CHDR Input Ports (from framework)
-  input  wire [(CHDR_W*${num_inputs})-1:0]  s_rfnoc_chdr_tdata,
-  input  wire [1:0]             s_rfnoc_chdr_tlast,
-  input  wire [1:0]             s_rfnoc_chdr_tvalid,
-  output wire [1:0]             s_rfnoc_chdr_tready,
-  // 2 CHDR Output Ports (to framework)
-  output wire [(CHDR_W*${num_outputs})-1:0]  m_rfnoc_chdr_tdata,
-  output wire [1:0]             m_rfnoc_chdr_tlast,
-  output wire [1:0]             m_rfnoc_chdr_tvalid,
-  input  wire [1:0]             m_rfnoc_chdr_tready,
+  // AXIS-CHDR Input Ports (from framework)
+  input  wire [(${func.num_ports_in_str()})*CHDR_W-1:0] s_rfnoc_chdr_tdata,
+  input  wire [(${func.num_ports_in_str()})-1:0]        s_rfnoc_chdr_tlast,
+  input  wire [(${func.num_ports_in_str()})-1:0]        s_rfnoc_chdr_tvalid,
+  output wire [(${func.num_ports_in_str()})-1:0]        s_rfnoc_chdr_tready,
+  // AXIS-CHDR Output Ports (to framework)
+  output wire [(${func.num_ports_out_str()})*CHDR_W-1:0] m_rfnoc_chdr_tdata,
+  output wire [(${func.num_ports_out_str()})-1:0]        m_rfnoc_chdr_tlast,
+  output wire [(${func.num_ports_out_str()})-1:0]        m_rfnoc_chdr_tvalid,
+  input  wire [(${func.num_ports_out_str()})-1:0]        m_rfnoc_chdr_tready,
   // AXIS-Ctrl Input Port (from framework)
   input  wire [31:0]            s_rfnoc_ctrl_tdata,
   input  wire                   s_rfnoc_ctrl_tlast,
@@ -55,97 +65,177 @@ module rfnoc_block_${config['module_name']} #(
   input  wire                   m_rfnoc_ctrl_tready
 );
 
-%for clock in config['clocks']:
-  %if clock['name'] in ["rfnoc_chdr", "rfnoc_ctrl"]:
-  wire ${clock['name']}_rst;
-  %endif
-%endfor
+  //---------------------------------------------------------------------------
+  // Signal Declarations
+  //---------------------------------------------------------------------------
 
+  // Clocks and Resets
+%if config['control']['fpga_iface'] == "ctrlport":
   wire               ctrlport_clk;
   wire               ctrlport_rst;
-
+%elif config['control']['fpga_iface'] == "axis_ctrl":
+  wire               axis_ctrl_clk;
+  wire               axis_ctrl_rst;
+%endif
+%if config['data']['fpga_iface'] == "axis_chdr":
+  wire               axis_chdr_clk;
+  wire               axis_chdr_rst;
+%elif config['data']['fpga_iface'] == "axis_pyld_ctxt":
   wire               axis_data_clk;
   wire               axis_data_rst;
+%elif config['data']['fpga_iface'] == "axis_data":
+  wire               axis_data_clk;
+  wire               axis_data_rst;
+%endif
+%if config['control']['fpga_iface'] == "ctrlport":
+<%include file="/modules/ctrlport_wires_template.mako" args="mode='block'"/>\
+%elif config['control']['fpga_iface'] == "axis_ctrl":
+<%include file="/modules/axis_ctrl_wires_template.mako" args="mode='block'"/>\
+%endif
+%if config['data']['fpga_iface'] == "axis_chdr":
+<%include file="/modules/axis_chdr_wires_template.mako" args="mode='block'"/>\
+%elif config['data']['fpga_iface'] == "axis_pyld_ctxt":
+<%include file="/modules/axis_pyld_ctxt_wires_template.mako" args="mode='block'"/>\
+%elif config['data']['fpga_iface'] == "axis_data":
+<%include file="/modules/axis_data_wires_template.mako" args="mode='block'"/>\
+%endif
+
+  //---------------------------------------------------------------------------
+  // NoC Shell
+  //---------------------------------------------------------------------------
+
+  noc_shell_${config['module_name']} #(
+    .CHDR_W      (CHDR_W),
+    .THIS_PORTID (THIS_PORTID),
+    .MTU         (MTU)
+  ) noc_shell_${config['module_name']}_i (
+    //---------------------
+    // Framework Interface
+    //---------------------
+
+    // Clock Inputs
+  %for clock in config['clocks']:
+    .${'{:<19}'.format(clock['name']+'_clk')} (${clock['name']}_clk),
+  %endfor
+    // Reset Outputs
+  %for clock in config['clocks']:
+    .${'{:<19}'.format(clock['name']+'_rst')} (),
+  %endfor
+    // RFNoC Backend Interface
+    .rfnoc_core_config   (rfnoc_core_config),
+    .rfnoc_core_status   (rfnoc_core_status),
+    // CHDR Input Ports  (from framework)
+    .s_rfnoc_chdr_tdata  (s_rfnoc_chdr_tdata),
+    .s_rfnoc_chdr_tlast  (s_rfnoc_chdr_tlast),
+    .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
+    .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
+    // CHDR Output Ports (to framework)
+    .m_rfnoc_chdr_tdata  (m_rfnoc_chdr_tdata),
+    .m_rfnoc_chdr_tlast  (m_rfnoc_chdr_tlast),
+    .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
+    .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
+    // AXIS-Ctrl Input Port (from framework)
+    .s_rfnoc_ctrl_tdata  (s_rfnoc_ctrl_tdata),
+    .s_rfnoc_ctrl_tlast  (s_rfnoc_ctrl_tlast),
+    .s_rfnoc_ctrl_tvalid (s_rfnoc_ctrl_tvalid),
+    .s_rfnoc_ctrl_tready (s_rfnoc_ctrl_tready),
+    // AXIS-Ctrl Output Port (to framework)
+    .m_rfnoc_ctrl_tdata  (m_rfnoc_ctrl_tdata),
+    .m_rfnoc_ctrl_tlast  (m_rfnoc_ctrl_tlast),
+    .m_rfnoc_ctrl_tvalid (m_rfnoc_ctrl_tvalid),
+    .m_rfnoc_ctrl_tready (m_rfnoc_ctrl_tready),
+
+    //---------------------
+    // Client Interface
+    //---------------------
 
 %if config['control']['fpga_iface'] == "ctrlport":
-<%include file="modules/ctrlport_wires_template.mako" args="mode='block'"/>
+<%include file="/modules/ctrlport_connect_template.mako"/>\
 %elif config['control']['fpga_iface'] == "axis_ctrl":
-<%include file="modules/axis_ctrl_wires_template.mako" args="mode='block'"/>
-%else:
-<%include file="control wires template.mako"/>
+<%include file="/modules/axis_ctrl_connect_template.mako"/>\
 %endif
 
 %if config['data']['fpga_iface'] == "axis_chdr":
-<%include file="modules/axis_chdr_wires_template.mako" args="mode='block', num_inputs=num_inputs, num_outputs=num_outputs"/>
-%elif config['data']['fpga_iface'] == "axis_rawdata":
-<%include file="modules/axis_raw_wires_template.mako" args="mode='block', num_inputs=num_inputs, num_outputs=num_outputs"/>
-%else:
-<%include file="data wires template.mako"/>
+<%include file="/modules/axis_chdr_connect_template.mako"/>\
+%elif config['data']['fpga_iface'] == "axis_pyld_ctxt":
+<%include file="/modules/axis_pyld_ctxt_connect_template.mako"/>\
+%elif config['data']['fpga_iface'] == "axis_data":
+<%include file="/modules/axis_data_connect_template.mako"/>\
 %endif
+  );
 
-//NoC Shell
-noc_shell_${config['module_name']} #(
-  .CHDR_W      (CHDR_W),
-  .THIS_PORTID (THIS_PORTID),
-  .MTU         (MTU)
-) noc_shell (
-%for clock in config['clocks']:
-  .${clock['name']}_clk(${clock['name']}_clk),
-  .${clock['name']}_rst(${clock['name']}_rst),
-%endfor
-
-  // RFNoC Backend Interface
-  .rfnoc_core_config(rfnoc_core_config),
-  .rfnoc_core_status(rfnoc_core_status),
-
-  // CHDR Input Ports (from framework)
-  .s_rfnoc_chdr_tdata(s_rfnoc_chdr_tdata),
-  .s_rfnoc_chdr_tlast(s_rfnoc_chdr_tlast),
-  .s_rfnoc_chdr_tvalid(s_rfnoc_chdr_tvalid),
-  .s_rfnoc_chdr_tready(s_rfnoc_chdr_tready),
-
-  // CHDR Output Ports (to framework)
-  .m_rfnoc_chdr_tdata(m_rfnoc_chdr_tdata),
-  .m_rfnoc_chdr_tlast(m_rfnoc_chdr_tlast),
-  .m_rfnoc_chdr_tvalid(m_rfnoc_chdr_tvalid),
-  .m_rfnoc_chdr_tready(m_rfnoc_chdr_tready),
-  // AXIS-Ctrl Input Port (from framework)
-  .s_rfnoc_ctrl_tdata(s_rfnoc_ctrl_tdata),
-  .s_rfnoc_ctrl_tlast(s_rfnoc_ctrl_tlast),
-  .s_rfnoc_ctrl_tvalid(s_rfnoc_ctrl_tvalid),
-  .s_rfnoc_ctrl_tready(s_rfnoc_ctrl_tready),
-  // AXIS-Ctrl Output Port (to framework)
-  .m_rfnoc_ctrl_tdata(m_rfnoc_ctrl_tdata),
-  .m_rfnoc_ctrl_tlast(m_rfnoc_ctrl_tlast),
-  .m_rfnoc_ctrl_tvalid(m_rfnoc_ctrl_tvalid),
-  .m_rfnoc_ctrl_tready(m_rfnoc_ctrl_tready),
+  //---------------------------------------------------------------------------
+  // User Logic
+  //---------------------------------------------------------------------------
 
-  // Client Interface
-  //------------------------------------------------------------
-  .ctrlport_clk(ctrlport_clk),
-  .ctrlport_rst(ctrlport_rst),
+  // < Replace this section with your logic >
 
+  // Nothing to do yet, so just drive control signals to default values
 %if config['control']['fpga_iface'] == "ctrlport":
-<%include file="modules/ctrlport_connect_template.mako"/>\
+  assign m_ctrlport_resp_ack = 1'b0;
+  %if config['control']['ctrlport']['has_status']:
+  assign m_ctrlport_resp_status = 2'b0;
+  %endif
+  %if config['control']['interface_direction'] != "slave":
+  assign s_ctrlport_req_wr = 1'b0;
+  assign s_ctrlport_req_rd = 1'b0;
+  %endif
 %elif config['control']['fpga_iface'] == "axis_ctrl":
-<%include file="modules/axis_ctrl_connect_template.mako"/>\
-%else:
-<%include file="control connect template.mako"/>\
+  assign m_axis_ctrl_tready = 1'b0;
+  assign s_axis_ctrl_tvalid = 1'b0;
 %endif
-
-  .axis_data_clk(axis_data_clk),
-  .axis_data_rst(axis_data_rst),
-
 %if config['data']['fpga_iface'] == "axis_chdr":
-<%include file="modules/axis_chdr_connect_template.mako" args="num_inputs=num_inputs, num_outputs=num_outputs"/>\
-%elif config['data']['fpga_iface'] == "axis_rawdata":
-<%include file="modules/axis_raw_connect_template.mako" args="num_inputs=num_inputs, num_outputs=num_outputs"/>\
-%else:
-<%include file="data connect template.mako"/>\
+  %for port_name, port_info in config['data']['inputs'].items():
+    %if 'num_ports' in port_info:
+  assign m_${port_name}_chdr_tready = {${port_info['num_ports']}{1'b0}};
+    %else:
+  assign m_${port_name}_chdr_tready = 1'b0;
+    %endif
+  %endfor
+  %for port_name, port_info in config['data']['outputs'].items():
+    %if 'num_ports' in port_info:
+  assign s_${port_name}_chdr_tvalid = {${port_info['num_ports']}{1'b0}};
+    %else:
+  assign s_${port_name}_chdr_tvalid = 1'b0;
+    %endif
+  %endfor
+%elif config['data']['fpga_iface'] == "axis_pyld_ctxt":
+  %for port_name, port_info in config['data']['inputs'].items():
+    %if 'num_ports' in port_info:
+  assign m_${port_name}_payload_tready = {${port_info['num_ports']}{1'b0}};
+  assign m_${port_name}_context_tready = {${port_info['num_ports']}{1'b0}};
+    %else:
+  assign m_${port_name}_payload_tready = 1'b0;
+  assign m_${port_name}_context_tready = 1'b0;
+    %endif
+  %endfor
+  %for port_name, port_info in config['data']['outputs'].items():
+    %if 'num_ports' in port_info:
+  assign s_${port_name}_payload_tvalid = {${port_info['num_ports']}{1'b0}};
+  assign s_${port_name}_context_tvalid = {${port_info['num_ports']}{1'b0}};
+    %else:
+  assign s_${port_name}_payload_tvalid = 1'b0;
+  assign s_${port_name}_context_tvalid = 1'b0;
+    %endif
+  %endfor
+%elif config['data']['fpga_iface'] == "axis_data":
+  %for port_name, port_info in config['data']['inputs'].items():
+    %if 'num_ports' in port_info:
+  assign m_${port_name}_axis_tready = {${port_info['num_ports']}{1'b0}};
+    %else:
+  assign m_${port_name}_axis_tready = 1'b0;
+    %endif
+  %endfor
+  %for port_name, port_info in config['data']['outputs'].items():
+    %if 'num_ports' in port_info:
+  assign s_${port_name}_axis_tvalid = {${port_info['num_ports']}{1'b0}};
+    %else:
+  assign s_${port_name}_axis_tvalid = 1'b0;
+    %endif
+  %endfor
 %endif
-);
 
+endmodule // rfnoc_block_${config['module_name']}
 
-//user code goes here
 
-endmodule // rfnoc_block_${config['module_name']}
+`default_nettype wire
diff --git a/host/utils/rfnoc_blocktool/templates/rfnoc_block_template_tb.sv.mako b/host/utils/rfnoc_blocktool/templates/rfnoc_block_template_tb.sv.mako
index 0bf4641b0..4ec1d1b93 100644
--- a/host/utils/rfnoc_blocktool/templates/rfnoc_block_template_tb.sv.mako
+++ b/host/utils/rfnoc_blocktool/templates/rfnoc_block_template_tb.sv.mako
@@ -1,3 +1,4 @@
+<%namespace name="func" file="/functions.mako"/>\
 //
 // Copyright 2019 Ettus Research, A National Instruments Company
 //
@@ -5,42 +6,53 @@
 //
 // Module: rfnoc_block_${config['module_name']}_tb
 //
+// Description: Testbench for the ${config['module_name']} RFNoC block.
+//
 
 `default_nettype none
 
 
 module rfnoc_block_${config['module_name']}_tb;
 
-  // Simulation Timing
-  timeunit 1ns;
-  timeprecision 1ps;
+  `include "test_exec.svh"
 
   import PkgTestExec::*;
   import PkgChdrUtils::*;
   import PkgRfnocBlockCtrlBfm::*;
   import PkgRfnocItemUtils::*;
 
-  // Parameters
-  localparam [9:0]  THIS_PORTID  = 10'h17;
-  localparam [15:0] THIS_EPID    = 16'hDEAD;
-  localparam int    CHDR_W       = 64;
-  localparam int    SPP          = 201;
-  localparam int    LPP          = ((SPP+1)/2);
-  localparam int    NUM_PKTS     = 50;
-
-  localparam int    PORT_SRCSNK  = 0;
-  localparam int    PORT_LOOP    = 1;
-
-  //adjust clocks to testbench needs
-  localparam int    CHDR_CLK_PER = 5; // 200 MHz
+  //---------------------------------------------------------------------------
+  // Testbench Configuration
+  //---------------------------------------------------------------------------
+
+  localparam [ 9:0] THIS_PORTID     = 10'h123;
+  localparam [31:0] NOC_ID          = 32'h${format(config['noc_id'], "08X")};
+  localparam int    CHDR_W          = ${config['chdr_width']};
+%if 'parameters' in config:
+%for param, value in config['parameters'].items():
+  localparam int    ${'{:<15}'.format(param)} = ${value};
+% endfor
+%endif
+  localparam int    NUM_PORTS_I     = ${func.num_ports_in_str()};
+  localparam int    NUM_PORTS_O     = ${func.num_ports_out_str()};
+  localparam int    MTU             = 13;
+  localparam int    SPP             = 64;
+  localparam int    PKT_SIZE_BYTES  = SPP * 4; // Assumes 4 bytes per sample
+  localparam int    STALL_PROB      = 25;      // Default BFM stall probability
+  localparam real   CHDR_CLK_PER    = 5.0;     // 200 MHz
+  localparam real   CTRL_CLK_PER    = 25.0;    // 40 MHz
 %for clock in config['clocks']:
   %if clock['name'] not in ["rfnoc_chdr", "rfnoc_ctrl"]:
-  localparam int    ${clock['name'].upper()}_CLK_PER = 5; // 200 MHz
+  localparam real   ${clock['name'].upper()}_CLK_PER = 5.0;  // 200 MHz
   %endif
 %endfor
 
-  // Clock and Reset Definition
+  //---------------------------------------------------------------------------
+  // Clocks and Resets
+  //---------------------------------------------------------------------------
+
   bit rfnoc_chdr_clk;
+  bit rfnoc_ctrl_clk;
 %for clock in config['clocks']:
   %if clock['name'] not in ["rfnoc_chdr", "rfnoc_ctrl"]:
   bit ${clock['name']}_clk;
@@ -48,82 +60,158 @@ module rfnoc_block_${config['module_name']}_tb;
 %endfor
 
   sim_clock_gen #(CHDR_CLK_PER) rfnoc_chdr_clk_gen (.clk(rfnoc_chdr_clk), .rst());
+  sim_clock_gen #(CTRL_CLK_PER) rfnoc_ctrl_clk_gen (.clk(rfnoc_ctrl_clk), .rst());
 %for clock in config['clocks']:
   %if clock['name'] not in ["rfnoc_chdr", "rfnoc_ctrl"]:
   sim_clock_gen #(${clock['name'].upper()}_CLK_PER) ${clock['name']}_clk_gen (.clk(${clock['name']}_clk), .rst());
   %endif
 %endfor
 
-  // ----------------------------------------
-  // Instantiate DUT
-  // ----------------------------------------
+  //---------------------------------------------------------------------------
+  // Bus Functional Models
+  //---------------------------------------------------------------------------
 
-  // Connections to DUT as interfaces:
-  RfnocBackendIf        backend (rfnoc_chdr_clk, rfnoc_chdr_clk); // Required backend iface
-  AxiStreamIf #(32)     m_ctrl  (rfnoc_chdr_clk);                 // Required control iface
-  AxiStreamIf #(32)     s_ctrl  (rfnoc_chdr_clk);                 // Required control iface
-  AxiStreamIf #(CHDR_W) m0_chdr (rfnoc_chdr_clk);                 // Optional data iface
-  AxiStreamIf #(CHDR_W) m1_chdr (rfnoc_chdr_clk);                 // Optional data iface
-  AxiStreamIf #(CHDR_W) s0_chdr (rfnoc_chdr_clk);                 // Optional data iface
-  AxiStreamIf #(CHDR_W) s1_chdr (rfnoc_chdr_clk);                 // Optional data iface
+  // Backend Interface
+  RfnocBackendIf backend (rfnoc_chdr_clk, rfnoc_ctrl_clk);
 
-  // Bus functional model for a software block controller
-  RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl;
+  // AXIS-Ctrl Interface
+  AxiStreamIf #(32) m_ctrl (rfnoc_ctrl_clk, 1'b0);
+  AxiStreamIf #(32) s_ctrl (rfnoc_ctrl_clk, 1'b0);
+
+  // AXIS-CHDR Interfaces
+  AxiStreamIf #(CHDR_W) m_chdr [NUM_PORTS_I] (rfnoc_chdr_clk, 1'b0);
+  AxiStreamIf #(CHDR_W) s_chdr [NUM_PORTS_O] (rfnoc_chdr_clk, 1'b0);
+
+  // Block Controller BFM
+  RfnocBlockCtrlBfm #(.CHDR_W(CHDR_W)) blk_ctrl = new(backend, m_ctrl, s_ctrl);
+
+  // Connect block controller to BFMs
+  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_bfm_input_connections
+    initial begin
+      blk_ctrl.connect_master_data_port(i, m_chdr[i], PKT_SIZE_BYTES);
+      blk_ctrl.set_master_stall_prob(i, STALL_PROB);
+    end
+  end
+  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_bfm_output_connections
+    initial begin
+      blk_ctrl.connect_slave_data_port(i, s_chdr[i]);
+      blk_ctrl.set_slave_stall_prob(i, STALL_PROB);
+    end
+  end
+
+  //---------------------------------------------------------------------------
+  // Device Under Test (DUT)
+  //---------------------------------------------------------------------------
+
+  // DUT Slave (Input) Port Signals
+  logic [CHDR_W*NUM_PORTS_I-1:0] s_rfnoc_chdr_tdata;
+  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tlast;
+  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tvalid;
+  logic [       NUM_PORTS_I-1:0] s_rfnoc_chdr_tready;
+
+  // DUT Master (Output) Port Signals
+  logic [CHDR_W*NUM_PORTS_O-1:0] m_rfnoc_chdr_tdata;
+  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tlast;
+  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tvalid;
+  logic [       NUM_PORTS_O-1:0] m_rfnoc_chdr_tready;
+
+  // Map the array of BFMs to a flat vector for the DUT connections
+  for (genvar i = 0; i < NUM_PORTS_I; i++) begin : gen_dut_input_connections
+    // Connect BFM master to DUT slave port
+    assign s_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W] = m_chdr[i].tdata;
+    assign s_rfnoc_chdr_tlast[i]                = m_chdr[i].tlast;
+    assign s_rfnoc_chdr_tvalid[i]               = m_chdr[i].tvalid;
+    assign m_chdr[i].tready                     = s_rfnoc_chdr_tready[i];
+  end
+  for (genvar i = 0; i < NUM_PORTS_O; i++) begin : gen_dut_output_connections
+    // Connect BFM slave to DUT master port
+    assign s_chdr[i].tdata        = m_rfnoc_chdr_tdata[CHDR_W*i+:CHDR_W];
+    assign s_chdr[i].tlast        = m_rfnoc_chdr_tlast[i];
+    assign s_chdr[i].tvalid       = m_rfnoc_chdr_tvalid[i];
+    assign m_rfnoc_chdr_tready[i] = s_chdr[i].tready;
+  end
 
-  // DUT
   rfnoc_block_${config['module_name']} #(
-    .THIS_PORTID        (THIS_PORTID),
-    .CHDR_W             (CHDR_W),
-    .MTU                (10)
+    .THIS_PORTID         (THIS_PORTID),
+    .CHDR_W              (CHDR_W),
+    .MTU                 (MTU)
   ) dut (
-    .rfnoc_chdr_clk     (backend.chdr_clk),
-    .rfnoc_ctrl_clk     (backend.ctrl_clk),
+    .rfnoc_chdr_clk      (rfnoc_chdr_clk),
+    .rfnoc_ctrl_clk      (rfnoc_ctrl_clk),
 %for clock in config['clocks']:
   %if clock['name'] not in ["rfnoc_chdr", "rfnoc_ctrl"]:
-    .${clock['name']}_clk(${clock['name']}_clk_gen.clk),
-    .${clock['name']}_rst(${clock['name']}_clk_gen.rst),
+    .${'{:<19}'.format(clock['name']+'_clk')} (${clock['name']}_clk),
   %endif
 %endfor
-    .rfnoc_core_config  (backend.cfg),
-    .rfnoc_core_status  (backend.sts),
-    .s_rfnoc_chdr_tdata ({m1_chdr.tdata  , m0_chdr.tdata  }),
-    .s_rfnoc_chdr_tlast ({m1_chdr.tlast  , m0_chdr.tlast  }),
-    .s_rfnoc_chdr_tvalid({m1_chdr.tvalid , m0_chdr.tvalid }),
-    .s_rfnoc_chdr_tready({m1_chdr.tready , m0_chdr.tready }),
-    .m_rfnoc_chdr_tdata ({s1_chdr.tdata , s0_chdr.tdata }),
-    .m_rfnoc_chdr_tlast ({s1_chdr.tlast , s0_chdr.tlast }),
-    .m_rfnoc_chdr_tvalid({s1_chdr.tvalid, s0_chdr.tvalid}),
-    .m_rfnoc_chdr_tready({s1_chdr.tready, s0_chdr.tready}),
-    .s_rfnoc_ctrl_tdata (m_ctrl.tdata  ),
-    .s_rfnoc_ctrl_tlast (m_ctrl.tlast  ),
-    .s_rfnoc_ctrl_tvalid(m_ctrl.tvalid ),
-    .s_rfnoc_ctrl_tready(m_ctrl.tready ),
-    .m_rfnoc_ctrl_tdata (s_ctrl.tdata ),
-    .m_rfnoc_ctrl_tlast (s_ctrl.tlast ),
-    .m_rfnoc_ctrl_tvalid(s_ctrl.tvalid),
-    .m_rfnoc_ctrl_tready(s_ctrl.tready)
+    .rfnoc_core_config   (backend.cfg),
+    .rfnoc_core_status   (backend.sts),
+    .s_rfnoc_chdr_tdata  (s_rfnoc_chdr_tdata),
+    .s_rfnoc_chdr_tlast  (s_rfnoc_chdr_tlast),
+    .s_rfnoc_chdr_tvalid (s_rfnoc_chdr_tvalid),
+    .s_rfnoc_chdr_tready (s_rfnoc_chdr_tready),
+    .m_rfnoc_chdr_tdata  (m_rfnoc_chdr_tdata),
+    .m_rfnoc_chdr_tlast  (m_rfnoc_chdr_tlast),
+    .m_rfnoc_chdr_tvalid (m_rfnoc_chdr_tvalid),
+    .m_rfnoc_chdr_tready (m_rfnoc_chdr_tready),
+    .s_rfnoc_ctrl_tdata  (m_ctrl.tdata),
+    .s_rfnoc_ctrl_tlast  (m_ctrl.tlast),
+    .s_rfnoc_ctrl_tvalid (m_ctrl.tvalid),
+    .s_rfnoc_ctrl_tready (m_ctrl.tready),
+    .m_rfnoc_ctrl_tdata  (s_ctrl.tdata),
+    .m_rfnoc_ctrl_tlast  (s_ctrl.tlast),
+    .m_rfnoc_ctrl_tvalid (s_ctrl.tvalid),
+    .m_rfnoc_ctrl_tready (s_ctrl.tready)
   );
 
-  // ----------------------------------------
-  // Test Process
-  // ----------------------------------------
-  TestExec test;
-  initial begin
-    // Shared Variables
-    // ----------------------------------------
-    timeout_t    timeout;
-    ctrl_word_t  rvalue;
-    rvalue = 0;
-
-    // Initialize
-    // ----------------------------------------
-    test = new("noc_block_${config['module_name']}_tb.v");
-    test.start_tb();
+  //---------------------------------------------------------------------------
+  // Main Test Process
+  //---------------------------------------------------------------------------
+
+  initial begin : tb_main
 
+    // Initialize the test exec object for this testbench
+    test.start_tb("rfnoc_block_${config['module_name']}_tb");
+
+    // Start the BFMs running
+    blk_ctrl.run();
+
+    //--------------------------------
+    // Reset
+    //--------------------------------
+
+    test.start_test("Flush block then reset it", 10us);
+    blk_ctrl.flush_and_reset();
+    test.end_test();
+
+    //--------------------------------
+    // Verify Block Info
+    //--------------------------------
+
+    test.start_test("Verify Block Info", 2us);
+    `ASSERT_ERROR(blk_ctrl.get_noc_id() == NOC_ID, "Incorrect NOC_ID Value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_i() == NUM_PORTS_I, "Incorrect NUM_DATA_I Value");
+    `ASSERT_ERROR(blk_ctrl.get_num_data_o() == NUM_PORTS_O, "Incorrect NUM_DATA_O Value");
+    `ASSERT_ERROR(blk_ctrl.get_mtu() == MTU, "Incorrect MTU Value");
+    test.end_test();
+
+    //--------------------------------
+    // Test Sequences
+    //--------------------------------
+
+    // <Add your test code here>
+    test.start_test("<Name your first test", 10us);
+    `ASSERT_WARNING(0, "This testbench doesn't test anything yet!");
+    test.end_test();
+
+    //--------------------------------
     // Finish Up
-    // ----------------------------------------
+    //--------------------------------
+
     // Display final statistics and results
     test.end_tb();
-  end
+  end : tb_main
+
+endmodule : rfnoc_block_${config['module_name']}_tb
+
 
-endmodule
+`default_nettype wire