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| author | Andrew Moch <Andrew.Moch@ni.com> | 2020-06-18 16:26:59 +0100 |
|---|---|---|
| committer | Wade Fife <wade.fife@ettus.com> | 2020-06-24 09:55:14 -0500 |
| commit | dd9847c5c3c3fac17658b526a7d8894711af086e (patch) | |
| tree | d4b4e41bdbe1f37b8c4c310770c2c552f862932a /host/tests | |
| parent | a3ff904432d831702d47534f37a437304f5c55c1 (diff) | |
| download | uhd-dd9847c5c3c3fac17658b526a7d8894711af086e.tar.gz uhd-dd9847c5c3c3fac17658b526a7d8894711af086e.tar.bz2 uhd-dd9847c5c3c3fac17658b526a7d8894711af086e.zip | |
fpga: lib: Pipeline and add clken to ip_hdr_checksum
Adds LATENCY parameter to control the ammount of pieplineing. Adds a
clock enable to control the advance of the pipeline.
Used in xport when calculating new UDP headers for CHDR traffic.
Diffstat (limited to 'host/tests')
0 files changed, 0 insertions, 0 deletions