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| author | Philip Balister <philip@opensdr.com> | 2010-11-09 18:13:25 -0800 |
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| committer | Philip Balister <philip@opensdr.com> | 2010-11-09 18:13:25 -0800 |
| commit | 7824f130bd1296c78f5b0311d1c253f0476c6cab (patch) | |
| tree | 22bd18d3d8f574d295232993633c0e56543915dd /host/test/vrt_test.cpp | |
| parent | bab641f4fdf954d6023904ca18c4bb4f6a362e47 (diff) | |
| download | uhd-7824f130bd1296c78f5b0311d1c253f0476c6cab.tar.gz uhd-7824f130bd1296c78f5b0311d1c253f0476c6cab.tar.bz2 uhd-7824f130bd1296c78f5b0311d1c253f0476c6cab.zip | |
usrp_e : Unload the module before loading the FPGA. Reload after the fpga is loaded.
Diffstat (limited to 'host/test/vrt_test.cpp')
0 files changed, 0 insertions, 0 deletions