e100: removed usrp from directory prefix

22 files changed, 520 insertions, 523 deletions

diff --git a/host/lib/usrp/CMakeLists.txt b/host/lib/usrp/CMakeLists.txt
index 80f4bf45e..45498e3b4 100644
--- a/host/lib/usrp/CMakeLists.txt
+++ b/host/lib/usrp/CMakeLists.txt
@@ -38,4 +38,4 @@ INCLUDE_SUBDIRECTORY(fx2)
 INCLUDE_SUBDIRECTORY(usrp1)
 INCLUDE_SUBDIRECTORY(usrp2)
 INCLUDE_SUBDIRECTORY(b100)
-INCLUDE_SUBDIRECTORY(usrp_e100)
+INCLUDE_SUBDIRECTORY(e100)
diff --git a/host/lib/usrp/b100/b100_ctrl.cpp b/host/lib/usrp/b100/b100_ctrl.cpp
index 2a87703f7..6d415facc 100644
--- a/host/lib/usrp/b100/b100_ctrl.cpp
+++ b/host/lib/usrp/b100/b100_ctrl.cpp
@@ -205,18 +205,15 @@ void b100_ctrl_impl::viking_marauder_loop(boost::barrier &spawn_barrier) {
                     time_t(if_packet_info.tsi), size_t(if_packet_info.tsf), 64e6 //FIXME get from clock_ctrl
                 );
                 metadata.event_code = async_metadata_t::event_code_t(sph::get_context_code(vrt_hdr, if_packet_info));
-                //print the famous U, and push the metadata into the message queue
-                if (metadata.event_code & 
+                async_msg_fifo.push_with_pop_on_full(metadata);
+                if (metadata.event_code &
                     ( async_metadata_t::EVENT_CODE_UNDERFLOW 
-                    | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET) )
-                    UHD_MSG(fastpath) << "U";
-                    
-                if (metadata.event_code & 
+                    | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET)
+                ) UHD_MSG(fastpath) << "U";
+                else if (metadata.event_code &
                     ( async_metadata_t::EVENT_CODE_SEQ_ERROR
-                    | async_metadata_t::EVENT_CODE_SEQ_ERROR_IN_BURST) )
-                    UHD_MSG(fastpath) << "S";
-                    
-                async_msg_fifo.push_with_pop_on_full(metadata);
+                    | async_metadata_t::EVENT_CODE_SEQ_ERROR_IN_BURST)
+                ) UHD_MSG(fastpath) << "S";
                 continue;
             }
             UHD_MSG(error) << "Control: unknown async response" << std::endl;
diff --git a/host/lib/usrp/usrp_e100/CMakeLists.txt b/host/lib/usrp/e100/CMakeLists.txt
index d0e20a3d8..15133ad5e 100644
--- a/host/lib/usrp/usrp_e100/CMakeLists.txt
+++ b/host/lib/usrp/e100/CMakeLists.txt
@@ -22,9 +22,9 @@
 ########################################################################
 # Conditionally configure the USRP-E100 support
 ########################################################################
-LIBUHD_REGISTER_COMPONENT("USRP-E100" ENABLE_USRP_E100 OFF "ENABLE_LIBUHD;LINUX" OFF)
+LIBUHD_REGISTER_COMPONENT("USRP-E100" ENABLE_E100 OFF "ENABLE_LIBUHD;LINUX" OFF)
 
-IF(ENABLE_USRP_E100)
+IF(ENABLE_E100)
     INCLUDE_DIRECTORIES(${CMAKE_CURRENT_SOURCE_DIR}/include)
 
     LIBUHD_APPEND_SOURCES(
@@ -39,11 +39,11 @@ IF(ENABLE_USRP_E100)
         ${CMAKE_CURRENT_SOURCE_DIR}/fpga_downloader.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/io_impl.cpp
         ${CMAKE_CURRENT_SOURCE_DIR}/mboard_impl.cpp
-        ${CMAKE_CURRENT_SOURCE_DIR}/usrp_e100_impl.cpp
-        ${CMAKE_CURRENT_SOURCE_DIR}/usrp_e100_impl.hpp
-        ${CMAKE_CURRENT_SOURCE_DIR}/usrp_e100_iface.cpp
-        ${CMAKE_CURRENT_SOURCE_DIR}/usrp_e100_iface.hpp
-        ${CMAKE_CURRENT_SOURCE_DIR}/usrp_e100_mmap_zero_copy.cpp
-        ${CMAKE_CURRENT_SOURCE_DIR}/usrp_e100_regs.hpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/e100_impl.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/e100_impl.hpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/e100_iface.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/e100_iface.hpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/e100_mmap_zero_copy.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/e100_regs.hpp
     )
-ENDIF(ENABLE_USRP_E100)
+ENDIF(ENABLE_E100)
diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.cpp b/host/lib/usrp/e100/clock_ctrl.cpp
index 742959ae3..ff64d9ca7 100644
--- a/host/lib/usrp/usrp_e100/clock_ctrl.cpp
+++ b/host/lib/usrp/e100/clock_ctrl.cpp
@@ -21,7 +21,7 @@
 #include <uhd/utils/log.hpp>
 #include <uhd/utils/assert_has.hpp>
 #include <boost/cstdint.hpp>
-#include "usrp_e100_regs.hpp" //spi slave constants
+#include "e100_regs.hpp" //spi slave constants
 #include <boost/assign/list_of.hpp>
 #include <boost/foreach.hpp>
 #include <boost/format.hpp>
@@ -165,9 +165,9 @@ static clock_settings_type get_clock_settings(double rate){
 /***********************************************************************
  * Clock Control Implementation
  **********************************************************************/
-class usrp_e100_clock_ctrl_impl : public usrp_e100_clock_ctrl{
+class e100_clock_ctrl_impl : public e100_clock_ctrl{
 public:
-    usrp_e100_clock_ctrl_impl(usrp_e100_iface::sptr iface, double master_clock_rate){
+    e100_clock_ctrl_impl(e100_iface::sptr iface, double master_clock_rate){
         _iface = iface;
         _chan_rate = 0.0;
         _out_rate = 0.0;
@@ -198,7 +198,7 @@ public:
         this->enable_tx_dboard_clock(false);
     }
 
-    ~usrp_e100_clock_ctrl_impl(void){
+    ~e100_clock_ctrl_impl(void){
         this->enable_test_clock(ENABLE_THE_TEST_OUT);
         this->enable_rx_dboard_clock(false);
         this->enable_tx_dboard_clock(false);
@@ -297,7 +297,7 @@ public:
         //clock rate changed! update dboard clocks and FPGA ticks per second
         set_rx_dboard_clock_rate(rate);
         set_tx_dboard_clock_rate(rate);
-        _iface->poke32(UE_REG_TIME64_TPS, boost::uint32_t(get_fpga_clock_rate()));
+        _iface->poke32(E100_REG_TIME64_TPS, boost::uint32_t(get_fpga_clock_rate()));
     }
 
     double get_fpga_clock_rate(void){
@@ -421,7 +421,7 @@ public:
     }
 
 private:
-    usrp_e100_iface::sptr _iface;
+    e100_iface::sptr _iface;
     ad9522_regs_t _ad9522_regs;
     double _out_rate; //rate at the fpga and codec
     double _chan_rate; //rate before final dividers
@@ -507,6 +507,6 @@ private:
 /***********************************************************************
  * Clock Control Make
  **********************************************************************/
-usrp_e100_clock_ctrl::sptr usrp_e100_clock_ctrl::make(usrp_e100_iface::sptr iface, double master_clock_rate){
-    return sptr(new usrp_e100_clock_ctrl_impl(iface, master_clock_rate));
+e100_clock_ctrl::sptr e100_clock_ctrl::make(e100_iface::sptr iface, double master_clock_rate){
+    return sptr(new e100_clock_ctrl_impl(iface, master_clock_rate));
 }
diff --git a/host/lib/usrp/usrp_e100/clock_ctrl.hpp b/host/lib/usrp/e100/clock_ctrl.hpp
index 6f16bc6ed..f3a6de0fa 100644
--- a/host/lib/usrp/usrp_e100/clock_ctrl.hpp
+++ b/host/lib/usrp/e100/clock_ctrl.hpp
@@ -18,7 +18,7 @@
 #ifndef INCLUDED_USRP_E100_CLOCK_CTRL_HPP
 #define INCLUDED_USRP_E100_CLOCK_CTRL_HPP
 
-#include "usrp_e100_iface.hpp"
+#include "e100_iface.hpp"
 #include <boost/shared_ptr.hpp>
 #include <boost/utility.hpp>
 #include <vector>
@@ -28,9 +28,9 @@
  * - Setup system clocks.
  * - Disable/enable clock lines.
  */
-class usrp_e100_clock_ctrl : boost::noncopyable{
+class e100_clock_ctrl : boost::noncopyable{
 public:
-    typedef boost::shared_ptr<usrp_e100_clock_ctrl> sptr;
+    typedef boost::shared_ptr<e100_clock_ctrl> sptr;
 
     /*!
      * Make a new clock control object.
@@ -38,7 +38,7 @@ public:
      * \param master clock rate the FPGA rate
      * \return the clock control object
      */
-    static sptr make(usrp_e100_iface::sptr iface, double master_clock_rate);
+    static sptr make(e100_iface::sptr iface, double master_clock_rate);
 
     /*!
      * Set the rate of the fpga clock line.
diff --git a/host/lib/usrp/usrp_e100/codec_ctrl.cpp b/host/lib/usrp/e100/codec_ctrl.cpp
index 43ad94a88..a796d5cc5 100644
--- a/host/lib/usrp/usrp_e100/codec_ctrl.cpp
+++ b/host/lib/usrp/e100/codec_ctrl.cpp
@@ -24,22 +24,22 @@
 #include <boost/cstdint.hpp>
 #include <boost/tuple/tuple.hpp>
 #include <boost/math/special_functions/round.hpp>
-#include "usrp_e100_regs.hpp" //spi slave constants
+#include "e100_regs.hpp" //spi slave constants
 #include <boost/assign/list_of.hpp>
 
 using namespace uhd;
 
-const gain_range_t usrp_e100_codec_ctrl::tx_pga_gain_range(-20, 0, double(0.1));
-const gain_range_t usrp_e100_codec_ctrl::rx_pga_gain_range(0, 20, 1);
+const gain_range_t e100_codec_ctrl::tx_pga_gain_range(-20, 0, double(0.1));
+const gain_range_t e100_codec_ctrl::rx_pga_gain_range(0, 20, 1);
 
 /***********************************************************************
  * Codec Control Implementation
  **********************************************************************/
-class usrp_e100_codec_ctrl_impl : public usrp_e100_codec_ctrl{
+class e100_codec_ctrl_impl : public e100_codec_ctrl{
 public:
     //structors
-    usrp_e100_codec_ctrl_impl(usrp_e100_iface::sptr iface);
-    ~usrp_e100_codec_ctrl_impl(void);
+    e100_codec_ctrl_impl(e100_iface::sptr iface);
+    ~e100_codec_ctrl_impl(void);
 
     //aux adc and dac control
     double read_aux_adc(aux_adc_t which);
@@ -52,7 +52,7 @@ public:
     double get_rx_pga_gain(char);
 
 private:
-    usrp_e100_iface::sptr _iface;
+    e100_iface::sptr _iface;
     ad9862_regs_t _ad9862_regs;
     void send_reg(boost::uint8_t addr);
     void recv_reg(boost::uint8_t addr);
@@ -61,7 +61,7 @@ private:
 /***********************************************************************
  * Codec Control Structors
  **********************************************************************/
-usrp_e100_codec_ctrl_impl::usrp_e100_codec_ctrl_impl(usrp_e100_iface::sptr iface){
+e100_codec_ctrl_impl::e100_codec_ctrl_impl(e100_iface::sptr iface){
     _iface = iface;
 
     //soft reset
@@ -116,7 +116,7 @@ usrp_e100_codec_ctrl_impl::usrp_e100_codec_ctrl_impl(usrp_e100_iface::sptr iface
     this->send_reg(34);
 }
 
-usrp_e100_codec_ctrl_impl::~usrp_e100_codec_ctrl_impl(void){
+e100_codec_ctrl_impl::~e100_codec_ctrl_impl(void){
     //set aux dacs to zero
     this->write_aux_dac(AUX_DAC_A, 0);
     this->write_aux_dac(AUX_DAC_B, 0);
@@ -136,19 +136,19 @@ usrp_e100_codec_ctrl_impl::~usrp_e100_codec_ctrl_impl(void){
  **********************************************************************/
 static const int mtpgw = 255; //maximum tx pga gain word
 
-void usrp_e100_codec_ctrl_impl::set_tx_pga_gain(double gain){
+void e100_codec_ctrl_impl::set_tx_pga_gain(double gain){
     int gain_word = int(mtpgw*(gain - tx_pga_gain_range.start())/(tx_pga_gain_range.stop() - tx_pga_gain_range.start()));
     _ad9862_regs.tx_pga_gain = uhd::clip(gain_word, 0, mtpgw);
     this->send_reg(16);
 }
 
-double usrp_e100_codec_ctrl_impl::get_tx_pga_gain(void){
+double e100_codec_ctrl_impl::get_tx_pga_gain(void){
     return (_ad9862_regs.tx_pga_gain*(tx_pga_gain_range.stop() - tx_pga_gain_range.start())/mtpgw) + tx_pga_gain_range.start();
 }
 
 static const int mrpgw = 0x14; //maximum rx pga gain word
 
-void usrp_e100_codec_ctrl_impl::set_rx_pga_gain(double gain, char which){
+void e100_codec_ctrl_impl::set_rx_pga_gain(double gain, char which){
     int gain_word = int(mrpgw*(gain - rx_pga_gain_range.start())/(rx_pga_gain_range.stop() - rx_pga_gain_range.start()));
     gain_word = uhd::clip(gain_word, 0, mrpgw);
     switch(which){
@@ -164,7 +164,7 @@ void usrp_e100_codec_ctrl_impl::set_rx_pga_gain(double gain, char which){
     }
 }
 
-double usrp_e100_codec_ctrl_impl::get_rx_pga_gain(char which){
+double e100_codec_ctrl_impl::get_rx_pga_gain(char which){
     int gain_word;
     switch(which){
     case 'A': gain_word = _ad9862_regs.rx_pga_a; break;
@@ -181,7 +181,7 @@ static double aux_adc_to_volts(boost::uint8_t high, boost::uint8_t low){
     return double((boost::uint16_t(high) << 2) | low)*3.3/0x3ff;
 }
 
-double usrp_e100_codec_ctrl_impl::read_aux_adc(aux_adc_t which){
+double e100_codec_ctrl_impl::read_aux_adc(aux_adc_t which){
     switch(which){
     case AUX_ADC_A1:
         _ad9862_regs.select_a = ad9862_regs_t::SELECT_A_AUX_ADC1;
@@ -217,7 +217,7 @@ double usrp_e100_codec_ctrl_impl::read_aux_adc(aux_adc_t which){
 /***********************************************************************
  * Codec Control AUX DAC Methods
  **********************************************************************/
-void usrp_e100_codec_ctrl_impl::write_aux_dac(aux_dac_t which, double volts){
+void e100_codec_ctrl_impl::write_aux_dac(aux_dac_t which, double volts){
     //special case for aux dac d (aka sigma delta word)
     if (which == AUX_DAC_D){
         boost::uint16_t dac_word = uhd::clip(boost::math::iround(volts*0xfff/3.3), 0, 0xfff);
@@ -250,7 +250,7 @@ void usrp_e100_codec_ctrl_impl::write_aux_dac(aux_dac_t which, double volts){
 /***********************************************************************
  * Codec Control SPI Methods
  **********************************************************************/
-void usrp_e100_codec_ctrl_impl::send_reg(boost::uint8_t addr){
+void e100_codec_ctrl_impl::send_reg(boost::uint8_t addr){
     boost::uint32_t reg = _ad9862_regs.get_write_reg(addr);
     UHD_LOGV(often) << "codec control write reg: " << std::hex << reg << std::endl;
     _iface->write_spi(
@@ -260,7 +260,7 @@ void usrp_e100_codec_ctrl_impl::send_reg(boost::uint8_t addr){
     );
 }
 
-void usrp_e100_codec_ctrl_impl::recv_reg(boost::uint8_t addr){
+void e100_codec_ctrl_impl::recv_reg(boost::uint8_t addr){
     boost::uint32_t reg = _ad9862_regs.get_read_reg(addr);
     UHD_LOGV(often) << "codec control read reg: " << std::hex << reg << std::endl;
     boost::uint32_t ret = _iface->read_spi(
@@ -275,6 +275,6 @@ void usrp_e100_codec_ctrl_impl::recv_reg(boost::uint8_t addr){
 /***********************************************************************
  * Codec Control Make
  **********************************************************************/
-usrp_e100_codec_ctrl::sptr usrp_e100_codec_ctrl::make(usrp_e100_iface::sptr iface){
-    return sptr(new usrp_e100_codec_ctrl_impl(iface));
+e100_codec_ctrl::sptr e100_codec_ctrl::make(e100_iface::sptr iface){
+    return sptr(new e100_codec_ctrl_impl(iface));
 }
diff --git a/host/lib/usrp/usrp_e100/codec_ctrl.hpp b/host/lib/usrp/e100/codec_ctrl.hpp
index 05d7aab38..22d0390f5 100644
--- a/host/lib/usrp/usrp_e100/codec_ctrl.hpp
+++ b/host/lib/usrp/e100/codec_ctrl.hpp
@@ -18,7 +18,7 @@
 #ifndef INCLUDED_USRP_E100_CODEC_CTRL_HPP
 #define INCLUDED_USRP_E100_CODEC_CTRL_HPP
 
-#include "usrp_e100_iface.hpp"
+#include "e100_iface.hpp"
 #include <uhd/types/ranges.hpp>
 #include <boost/shared_ptr.hpp>
 #include <boost/utility.hpp>
@@ -28,9 +28,9 @@
  * - Init/power down codec.
  * - Read aux adc, write aux dac.
  */
-class usrp_e100_codec_ctrl : boost::noncopyable{
+class e100_codec_ctrl : boost::noncopyable{
 public:
-    typedef boost::shared_ptr<usrp_e100_codec_ctrl> sptr;
+    typedef boost::shared_ptr<e100_codec_ctrl> sptr;
 
     static const uhd::gain_range_t tx_pga_gain_range;
     static const uhd::gain_range_t rx_pga_gain_range;
@@ -40,7 +40,7 @@ public:
      * \param iface the usrp_e100 iface object
      * \return the codec control object
      */
-    static sptr make(usrp_e100_iface::sptr iface);
+    static sptr make(e100_iface::sptr iface);
 
     //! aux adc identifier constants
     enum aux_adc_t{
diff --git a/host/lib/usrp/usrp_e100/codec_impl.cpp b/host/lib/usrp/e100/codec_impl.cpp
index ae198aaa5..26743d173 100644
--- a/host/lib/usrp/usrp_e100/codec_impl.cpp
+++ b/host/lib/usrp/e100/codec_impl.cpp
@@ -15,7 +15,7 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-#include "usrp_e100_impl.hpp"
+#include "e100_impl.hpp"
 #include <uhd/exception.hpp>
 #include <uhd/usrp/codec_props.hpp>
 #include <boost/bind.hpp>
@@ -26,15 +26,15 @@ using namespace uhd::usrp;
 /***********************************************************************
  * Helper Methods
  **********************************************************************/
-void usrp_e100_impl::codec_init(void){
+void e100_impl::codec_init(void){
     //make proxies
     _rx_codec_proxy = wax_obj_proxy::make(
-        boost::bind(&usrp_e100_impl::rx_codec_get, this, _1, _2),
-        boost::bind(&usrp_e100_impl::rx_codec_set, this, _1, _2)
+        boost::bind(&e100_impl::rx_codec_get, this, _1, _2),
+        boost::bind(&e100_impl::rx_codec_set, this, _1, _2)
     );
     _tx_codec_proxy = wax_obj_proxy::make(
-        boost::bind(&usrp_e100_impl::tx_codec_get, this, _1, _2),
-        boost::bind(&usrp_e100_impl::tx_codec_set, this, _1, _2)
+        boost::bind(&e100_impl::tx_codec_get, this, _1, _2),
+        boost::bind(&e100_impl::tx_codec_set, this, _1, _2)
     );
 }
 
@@ -43,7 +43,7 @@ void usrp_e100_impl::codec_init(void){
  **********************************************************************/
 static const std::string ad9862_pga_gain_name = "ad9862 pga";
 
-void usrp_e100_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){
+void e100_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){
     named_prop_t key = named_prop_t::extract(key_);
 
     //handle the get request conditioned on the key
@@ -62,7 +62,7 @@ void usrp_e100_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){
 
     case CODEC_PROP_GAIN_RANGE:
         UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name);
-        val = usrp_e100_codec_ctrl::rx_pga_gain_range;
+        val = e100_codec_ctrl::rx_pga_gain_range;
         return;
 
     case CODEC_PROP_GAIN_I:
@@ -79,7 +79,7 @@ void usrp_e100_impl::rx_codec_get(const wax::obj &key_, wax::obj &val){
     }
 }
 
-void usrp_e100_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){
+void e100_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){
     named_prop_t key = named_prop_t::extract(key_);
 
     //handle the set request conditioned on the key
@@ -101,7 +101,7 @@ void usrp_e100_impl::rx_codec_set(const wax::obj &key_, const wax::obj &val){
 /***********************************************************************
  * TX Codec Properties
  **********************************************************************/
-void usrp_e100_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){
+void e100_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){
     named_prop_t key = named_prop_t::extract(key_);
 
     //handle the get request conditioned on the key
@@ -120,7 +120,7 @@ void usrp_e100_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){
 
     case CODEC_PROP_GAIN_RANGE:
         UHD_ASSERT_THROW(key.name == ad9862_pga_gain_name);
-        val = usrp_e100_codec_ctrl::tx_pga_gain_range;
+        val = e100_codec_ctrl::tx_pga_gain_range;
         return;
 
     case CODEC_PROP_GAIN_I: //only one gain for I and Q
@@ -133,7 +133,7 @@ void usrp_e100_impl::tx_codec_get(const wax::obj &key_, wax::obj &val){
     }
 }
 
-void usrp_e100_impl::tx_codec_set(const wax::obj &key_, const wax::obj &val){
+void e100_impl::tx_codec_set(const wax::obj &key_, const wax::obj &val){
     named_prop_t key = named_prop_t::extract(key_);
 
     //handle the set request conditioned on the key
diff --git a/host/lib/usrp/usrp_e100/dboard_iface.cpp b/host/lib/usrp/e100/dboard_iface.cpp
index 61b5a1c92..43e05aa57 100644
--- a/host/lib/usrp/usrp_e100/dboard_iface.cpp
+++ b/host/lib/usrp/e100/dboard_iface.cpp
@@ -15,8 +15,8 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-#include "usrp_e100_iface.hpp"
-#include "usrp_e100_regs.hpp"
+#include "e100_iface.hpp"
+#include "e100_regs.hpp"
 #include "clock_ctrl.hpp"
 #include "codec_ctrl.hpp"
 #include <uhd/usrp/dboard_iface.hpp>
@@ -33,9 +33,9 @@ class usrp_e100_dboard_iface : public dboard_iface{
 public:
 
     usrp_e100_dboard_iface(
-        usrp_e100_iface::sptr iface,
-        usrp_e100_clock_ctrl::sptr clock,
-        usrp_e100_codec_ctrl::sptr codec
+        e100_iface::sptr iface,
+        e100_clock_ctrl::sptr clock,
+        e100_codec_ctrl::sptr codec
     ){
         _iface = iface;
         _clock = clock;
@@ -45,8 +45,8 @@ public:
         this->set_clock_rate(UNIT_RX, _clock->get_fpga_clock_rate());
         this->set_clock_rate(UNIT_TX, _clock->get_fpga_clock_rate());
 
-        _iface->poke16(UE_REG_GPIO_RX_DBG, 0);
-        _iface->poke16(UE_REG_GPIO_TX_DBG, 0);
+        _iface->poke16(E100_REG_GPIO_RX_DBG, 0);
+        _iface->poke16(E100_REG_GPIO_TX_DBG, 0);
     }
 
     ~usrp_e100_dboard_iface(void){
@@ -94,18 +94,18 @@ public:
     double get_codec_rate(unit_t);
 
 private:
-    usrp_e100_iface::sptr _iface;
-    usrp_e100_clock_ctrl::sptr _clock;
-    usrp_e100_codec_ctrl::sptr _codec;
+    e100_iface::sptr _iface;
+    e100_clock_ctrl::sptr _clock;
+    e100_codec_ctrl::sptr _codec;
 };
 
 /***********************************************************************
  * Make Function
  **********************************************************************/
 dboard_iface::sptr make_usrp_e100_dboard_iface(
-    usrp_e100_iface::sptr iface,
-    usrp_e100_clock_ctrl::sptr clock,
-    usrp_e100_codec_ctrl::sptr codec
+    e100_iface::sptr iface,
+    e100_clock_ctrl::sptr clock,
+    e100_codec_ctrl::sptr codec
 ){
     return dboard_iface::sptr(new usrp_e100_dboard_iface(iface, clock, codec));
 }
@@ -153,29 +153,29 @@ double usrp_e100_dboard_iface::get_codec_rate(unit_t){
 void usrp_e100_dboard_iface::_set_pin_ctrl(unit_t unit, boost::uint16_t value){
     UHD_ASSERT_THROW(GPIO_SEL_ATR == 1); //make this assumption
     switch(unit){
-    case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_SEL, value); return;
-    case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_SEL, value); return;
+    case UNIT_RX: _iface->poke16(E100_REG_GPIO_RX_SEL, value); return;
+    case UNIT_TX: _iface->poke16(E100_REG_GPIO_TX_SEL, value); return;
     }
 }
 
 void usrp_e100_dboard_iface::_set_gpio_ddr(unit_t unit, boost::uint16_t value){
     switch(unit){
-    case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_DDR, value); return;
-    case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_DDR, value); return;
+    case UNIT_RX: _iface->poke16(E100_REG_GPIO_RX_DDR, value); return;
+    case UNIT_TX: _iface->poke16(E100_REG_GPIO_TX_DDR, value); return;
     }
 }
 
 void usrp_e100_dboard_iface::_set_gpio_out(unit_t unit, boost::uint16_t value){
     switch(unit){
-    case UNIT_RX: _iface->poke16(UE_REG_GPIO_RX_IO, value); return;
-    case UNIT_TX: _iface->poke16(UE_REG_GPIO_TX_IO, value); return;
+    case UNIT_RX: _iface->poke16(E100_REG_GPIO_RX_IO, value); return;
+    case UNIT_TX: _iface->poke16(E100_REG_GPIO_TX_IO, value); return;
     }
 }
 
 boost::uint16_t usrp_e100_dboard_iface::read_gpio(unit_t unit){
     switch(unit){
-    case UNIT_RX: return _iface->peek16(UE_REG_GPIO_RX_IO);
-    case UNIT_TX: return _iface->peek16(UE_REG_GPIO_TX_IO);
+    case UNIT_RX: return _iface->peek16(E100_REG_GPIO_RX_IO);
+    case UNIT_TX: return _iface->peek16(E100_REG_GPIO_TX_IO);
     default: UHD_THROW_INVALID_CODE_PATH();
     }
 }
@@ -186,16 +186,16 @@ void usrp_e100_dboard_iface::_set_atr_reg(unit_t unit, atr_reg_t atr, boost::uin
         unit_t, uhd::dict<atr_reg_t, boost::uint32_t>
     > unit_to_atr_to_addr = map_list_of
         (UNIT_RX, map_list_of
-            (ATR_REG_IDLE,        UE_REG_ATR_IDLE_RXSIDE)
-            (ATR_REG_TX_ONLY,     UE_REG_ATR_INTX_RXSIDE)
-            (ATR_REG_RX_ONLY,     UE_REG_ATR_INRX_RXSIDE)
-            (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_RXSIDE)
+            (ATR_REG_IDLE,        E100_REG_ATR_IDLE_RXSIDE)
+            (ATR_REG_TX_ONLY,     E100_REG_ATR_INTX_RXSIDE)
+            (ATR_REG_RX_ONLY,     E100_REG_ATR_INRX_RXSIDE)
+            (ATR_REG_FULL_DUPLEX, E100_REG_ATR_FULL_RXSIDE)
         )
         (UNIT_TX, map_list_of
-            (ATR_REG_IDLE,        UE_REG_ATR_IDLE_TXSIDE)
-            (ATR_REG_TX_ONLY,     UE_REG_ATR_INTX_TXSIDE)
-            (ATR_REG_RX_ONLY,     UE_REG_ATR_INRX_TXSIDE)
-            (ATR_REG_FULL_DUPLEX, UE_REG_ATR_FULL_TXSIDE)
+            (ATR_REG_IDLE,        E100_REG_ATR_IDLE_TXSIDE)
+            (ATR_REG_TX_ONLY,     E100_REG_ATR_INTX_TXSIDE)
+            (ATR_REG_RX_ONLY,     E100_REG_ATR_INRX_TXSIDE)
+            (ATR_REG_FULL_DUPLEX, E100_REG_ATR_FULL_TXSIDE)
         )
     ;
     _iface->poke16(unit_to_atr_to_addr[unit][atr], value);
@@ -213,13 +213,13 @@ void usrp_e100_dboard_iface::set_gpio_debug(unit_t unit, int which){
     //set the debug on and which debug selection
     switch(unit){
     case UNIT_RX:
-        _iface->poke16(UE_REG_GPIO_RX_DBG, 0xffff);
-        _iface->poke16(UE_REG_GPIO_RX_SEL, dbg_sels);
+        _iface->poke16(E100_REG_GPIO_RX_DBG, 0xffff);
+        _iface->poke16(E100_REG_GPIO_RX_SEL, dbg_sels);
         return;
 
     case UNIT_TX:
-        _iface->poke16(UE_REG_GPIO_TX_DBG, 0xffff);
-        _iface->poke16(UE_REG_GPIO_TX_SEL, dbg_sels);
+        _iface->poke16(E100_REG_GPIO_TX_DBG, 0xffff);
+        _iface->poke16(E100_REG_GPIO_TX_SEL, dbg_sels);
         return;
     }
 }
@@ -274,26 +274,26 @@ byte_vector_t usrp_e100_dboard_iface::read_i2c(boost::uint8_t addr, size_t num_b
  **********************************************************************/
 void usrp_e100_dboard_iface::write_aux_dac(dboard_iface::unit_t, aux_dac_t which, double value){
     //same aux dacs for each unit
-    static const uhd::dict<aux_dac_t, usrp_e100_codec_ctrl::aux_dac_t> which_to_aux_dac = map_list_of
-        (AUX_DAC_A, usrp_e100_codec_ctrl::AUX_DAC_A)
-        (AUX_DAC_B, usrp_e100_codec_ctrl::AUX_DAC_B)
-        (AUX_DAC_C, usrp_e100_codec_ctrl::AUX_DAC_C)
-        (AUX_DAC_D, usrp_e100_codec_ctrl::AUX_DAC_D)
+    static const uhd::dict<aux_dac_t, e100_codec_ctrl::aux_dac_t> which_to_aux_dac = map_list_of
+        (AUX_DAC_A, e100_codec_ctrl::AUX_DAC_A)
+        (AUX_DAC_B, e100_codec_ctrl::AUX_DAC_B)
+        (AUX_DAC_C, e100_codec_ctrl::AUX_DAC_C)
+        (AUX_DAC_D, e100_codec_ctrl::AUX_DAC_D)
     ;
     _codec->write_aux_dac(which_to_aux_dac[which], value);
 }
 
 double usrp_e100_dboard_iface::read_aux_adc(dboard_iface::unit_t unit, aux_adc_t which){
     static const uhd::dict<
-        unit_t, uhd::dict<aux_adc_t, usrp_e100_codec_ctrl::aux_adc_t>
+        unit_t, uhd::dict<aux_adc_t, e100_codec_ctrl::aux_adc_t>
     > unit_to_which_to_aux_adc = map_list_of
         (UNIT_RX, map_list_of
-            (AUX_ADC_A, usrp_e100_codec_ctrl::AUX_ADC_A1)
-            (AUX_ADC_B, usrp_e100_codec_ctrl::AUX_ADC_B1)
+            (AUX_ADC_A, e100_codec_ctrl::AUX_ADC_A1)
+            (AUX_ADC_B, e100_codec_ctrl::AUX_ADC_B1)
         )
         (UNIT_TX, map_list_of
-            (AUX_ADC_A, usrp_e100_codec_ctrl::AUX_ADC_A2)
-            (AUX_ADC_B, usrp_e100_codec_ctrl::AUX_ADC_B2)
+            (AUX_ADC_A, e100_codec_ctrl::AUX_ADC_A2)
+            (AUX_ADC_B, e100_codec_ctrl::AUX_ADC_B2)
         )
     ;
     return _codec->read_aux_adc(unit_to_which_to_aux_adc[unit][which]);
diff --git a/host/lib/usrp/usrp_e100/dboard_impl.cpp b/host/lib/usrp/e100/dboard_impl.cpp
index f6bbbd5e8..86481e70a 100644
--- a/host/lib/usrp/usrp_e100/dboard_impl.cpp
+++ b/host/lib/usrp/e100/dboard_impl.cpp
@@ -15,8 +15,8 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-#include "usrp_e100_impl.hpp"
-#include "usrp_e100_regs.hpp"
+#include "e100_impl.hpp"
+#include "e100_regs.hpp"
 #include <uhd/exception.hpp>
 #include <uhd/usrp/dboard_props.hpp>
 #include <uhd/usrp/subdev_props.hpp>
@@ -30,7 +30,7 @@ using namespace uhd::usrp;
 /***********************************************************************
  * Dboard Initialization
  **********************************************************************/
-void usrp_e100_impl::dboard_init(void){
+void e100_impl::dboard_init(void){
     //read the dboard eeprom to extract the dboard ids
     _rx_db_eeprom.load(*_iface, I2C_ADDR_RX_DB);
     _tx_db_eeprom.load(*_iface, I2C_ADDR_TX_DB);
@@ -48,19 +48,19 @@ void usrp_e100_impl::dboard_init(void){
 
     //setup the dboard proxies
     _rx_dboard_proxy = wax_obj_proxy::make(
-        boost::bind(&usrp_e100_impl::rx_dboard_get, this, _1, _2),
-        boost::bind(&usrp_e100_impl::rx_dboard_set, this, _1, _2)
+        boost::bind(&e100_impl::rx_dboard_get, this, _1, _2),
+        boost::bind(&e100_impl::rx_dboard_set, this, _1, _2)
     );
     _tx_dboard_proxy = wax_obj_proxy::make(
-        boost::bind(&usrp_e100_impl::tx_dboard_get, this, _1, _2),
-        boost::bind(&usrp_e100_impl::tx_dboard_set, this, _1, _2)
+        boost::bind(&e100_impl::tx_dboard_get, this, _1, _2),
+        boost::bind(&e100_impl::tx_dboard_set, this, _1, _2)
     );
 }
 
 /***********************************************************************
  * RX Dboard Get
  **********************************************************************/
-void usrp_e100_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){
+void e100_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){
     named_prop_t key = named_prop_t::extract(key_);
 
     //handle the get request conditioned on the key
@@ -105,7 +105,7 @@ void usrp_e100_impl::rx_dboard_get(const wax::obj &key_, wax::obj &val){
 /***********************************************************************
  * RX Dboard Set
  **********************************************************************/
-void usrp_e100_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){
+void e100_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){
     switch(key.as<dboard_prop_t>()){
     case DBOARD_PROP_DBOARD_EEPROM:
         _rx_db_eeprom = val.as<dboard_eeprom_t>();
@@ -119,7 +119,7 @@ void usrp_e100_impl::rx_dboard_set(const wax::obj &key, const wax::obj &val){
 /***********************************************************************
  * TX Dboard Get
  **********************************************************************/
-void usrp_e100_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){
+void e100_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){
     named_prop_t key = named_prop_t::extract(key_);
 
     //handle the get request conditioned on the key
@@ -168,7 +168,7 @@ void usrp_e100_impl::tx_dboard_get(const wax::obj &key_, wax::obj &val){
 /***********************************************************************
  * TX Dboard Set
  **********************************************************************/
-void usrp_e100_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){
+void e100_impl::tx_dboard_set(const wax::obj &key, const wax::obj &val){
     switch(key.as<dboard_prop_t>()){
     case DBOARD_PROP_DBOARD_EEPROM:
         _tx_db_eeprom = val.as<dboard_eeprom_t>();
diff --git a/host/lib/usrp/usrp_e100/dsp_impl.cpp b/host/lib/usrp/e100/dsp_impl.cpp
index 57bfdc3c4..fc65609a0 100644
--- a/host/lib/usrp/usrp_e100/dsp_impl.cpp
+++ b/host/lib/usrp/e100/dsp_impl.cpp
@@ -15,8 +15,8 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-#include "usrp_e100_impl.hpp"
-#include "usrp_e100_regs.hpp"
+#include "e100_impl.hpp"
+#include "e100_regs.hpp"
 #include <uhd/usrp/dsp_utils.hpp>
 #include <uhd/usrp/dsp_props.hpp>
 #include <boost/math/special_functions/round.hpp>
@@ -28,7 +28,7 @@ using namespace uhd::usrp;
 /***********************************************************************
  * DSP impl and methods
  **********************************************************************/
-struct usrp_e100_impl::dsp_impl{
+struct e100_impl::dsp_impl{
     uhd::dict<size_t, size_t> ddc_decim;
     uhd::dict<size_t, double> ddc_freq;
     uhd::dict<size_t, size_t> duc_interp;
@@ -38,15 +38,15 @@ struct usrp_e100_impl::dsp_impl{
 /***********************************************************************
  * RX DDC Initialization
  **********************************************************************/
-void usrp_e100_impl::dsp_init(void){
+void e100_impl::dsp_init(void){
     //create new dsp impl
     _dsp_impl = UHD_PIMPL_MAKE(dsp_impl, ());
 
     //bind and initialize the rx dsps
     for (size_t i = 0; i < E100_NUM_RX_DSPS; i++){
         _rx_dsp_proxies[str(boost::format("DSP%d")%i)] = wax_obj_proxy::make(
-            boost::bind(&usrp_e100_impl::ddc_get, this, _1, _2, i),
-            boost::bind(&usrp_e100_impl::ddc_set, this, _1, _2, i)
+            boost::bind(&e100_impl::ddc_get, this, _1, _2, i),
+            boost::bind(&e100_impl::ddc_set, this, _1, _2, i)
         );
 
         //initial config and update
@@ -54,25 +54,25 @@ void usrp_e100_impl::dsp_init(void){
         ddc_set(DSP_PROP_HOST_RATE, double(_clock_ctrl->get_fpga_clock_rate()/16), i);
 
         //setup the rx control registers
-        _iface->poke32(UE_REG_RX_CTRL_CLEAR(i), 1); //reset
-        _iface->poke32(UE_REG_RX_CTRL_NSAMPS_PP(i), this->get_max_recv_samps_per_packet());
-        _iface->poke32(UE_REG_RX_CTRL_NCHANNELS(i), 1);
-        _iface->poke32(UE_REG_RX_CTRL_VRT_HDR(i), 0
+        _iface->poke32(E100_REG_RX_CTRL_CLEAR(i), 1); //reset
+        _iface->poke32(E100_REG_RX_CTRL_NSAMPS_PP(i), this->get_max_recv_samps_per_packet());
+        _iface->poke32(E100_REG_RX_CTRL_NCHANNELS(i), 1);
+        _iface->poke32(E100_REG_RX_CTRL_VRT_HDR(i), 0
             | (0x1 << 28) //if data with stream id
             | (0x1 << 26) //has trailer
             | (0x3 << 22) //integer time other
             | (0x1 << 20) //fractional time sample count
         );
-        _iface->poke32(UE_REG_RX_CTRL_VRT_SID(i), E100_DSP_SID_BASE + i);
-        _iface->poke32(UE_REG_RX_CTRL_VRT_TLR(i), 0);
-        _iface->poke32(UE_REG_TIME64_TPS, size_t(_clock_ctrl->get_fpga_clock_rate()));
+        _iface->poke32(E100_REG_RX_CTRL_VRT_SID(i), E100_DSP_SID_BASE + i);
+        _iface->poke32(E100_REG_RX_CTRL_VRT_TLR(i), 0);
+        _iface->poke32(E100_REG_TIME64_TPS, size_t(_clock_ctrl->get_fpga_clock_rate()));
     }
 
     //bind and initialize the tx dsps
     for (size_t i = 0; i < E100_NUM_TX_DSPS; i++){
         _tx_dsp_proxies[str(boost::format("DSP%d")%i)] = wax_obj_proxy::make(
-            boost::bind(&usrp_e100_impl::duc_get, this, _1, _2, i),
-            boost::bind(&usrp_e100_impl::duc_set, this, _1, _2, i)
+            boost::bind(&e100_impl::duc_get, this, _1, _2, i),
+            boost::bind(&e100_impl::duc_set, this, _1, _2, i)
         );
 
         //initial config and update
@@ -80,17 +80,17 @@ void usrp_e100_impl::dsp_init(void){
         duc_set(DSP_PROP_HOST_RATE, double(_clock_ctrl->get_fpga_clock_rate()/16), i);
 
         //init the tx control registers
-        _iface->poke32(UE_REG_TX_CTRL_CLEAR_STATE, 1); //reset
-        _iface->poke32(UE_REG_TX_CTRL_NUM_CHAN, 0);    //1 channel
-        _iface->poke32(UE_REG_TX_CTRL_REPORT_SID, E100_ASYNC_SID);
-        _iface->poke32(UE_REG_TX_CTRL_POLICY, UE_FLAG_TX_CTRL_POLICY_NEXT_PACKET);
+        _iface->poke32(E100_REG_TX_CTRL_CLEAR_STATE, 1); //reset
+        _iface->poke32(E100_REG_TX_CTRL_NUM_CHAN, 0);    //1 channel
+        _iface->poke32(E100_REG_TX_CTRL_REPORT_SID, E100_ASYNC_SID);
+        _iface->poke32(E100_REG_TX_CTRL_POLICY, E100_FLAG_TX_CTRL_POLICY_NEXT_PACKET);
     }
 }
 
 /***********************************************************************
  * RX DDC Get
  **********************************************************************/
-void usrp_e100_impl::ddc_get(const wax::obj &key_, wax::obj &val, size_t which_dsp){
+void e100_impl::ddc_get(const wax::obj &key_, wax::obj &val, size_t which_dsp){
     named_prop_t key = named_prop_t::extract(key_);
 
     switch(key.as<dsp_prop_t>()){
@@ -121,7 +121,7 @@ void usrp_e100_impl::ddc_get(const wax::obj &key_, wax::obj &val, size_t which_d
 /***********************************************************************
  * RX DDC Set
  **********************************************************************/
-void usrp_e100_impl::ddc_set(const wax::obj &key_, const wax::obj &val, size_t which_dsp){
+void e100_impl::ddc_set(const wax::obj &key_, const wax::obj &val, size_t which_dsp){
     named_prop_t key = named_prop_t::extract(key_);
 
     switch(key.as<dsp_prop_t>()){
@@ -132,7 +132,7 @@ void usrp_e100_impl::ddc_set(const wax::obj &key_, const wax::obj &val, size_t w
 
     case DSP_PROP_FREQ_SHIFT:{
             double new_freq = val.as<double>();
-            _iface->poke32(UE_REG_DSP_RX_FREQ(which_dsp),
+            _iface->poke32(E100_REG_DSP_RX_FREQ(which_dsp),
                 dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate())
             );
             _dsp_impl->ddc_freq[which_dsp] = new_freq; //shadow
@@ -143,7 +143,7 @@ void usrp_e100_impl::ddc_set(const wax::obj &key_, const wax::obj &val, size_t w
             _dsp_impl->ddc_decim[which_dsp] = boost::math::iround(_clock_ctrl->get_fpga_clock_rate()/val.as<double>());
 
             //set the decimation
-            _iface->poke32(UE_REG_DSP_RX_DECIM(which_dsp), dsp_type1::calc_cic_filter_word(_dsp_impl->ddc_decim[which_dsp]));
+            _iface->poke32(E100_REG_DSP_RX_DECIM(which_dsp), dsp_type1::calc_cic_filter_word(_dsp_impl->ddc_decim[which_dsp]));
         }
         this->update_xport_channel_mapping(); //rate changed -> update
         return;
@@ -155,7 +155,7 @@ void usrp_e100_impl::ddc_set(const wax::obj &key_, const wax::obj &val, size_t w
 /***********************************************************************
  * TX DUC Get
  **********************************************************************/
-void usrp_e100_impl::duc_get(const wax::obj &key_, wax::obj &val, size_t which_dsp){
+void e100_impl::duc_get(const wax::obj &key_, wax::obj &val, size_t which_dsp){
     named_prop_t key = named_prop_t::extract(key_);
 
     switch(key.as<dsp_prop_t>()){
@@ -186,14 +186,14 @@ void usrp_e100_impl::duc_get(const wax::obj &key_, wax::obj &val, size_t which_d
 /***********************************************************************
  * TX DUC Set
  **********************************************************************/
-void usrp_e100_impl::duc_set(const wax::obj &key_, const wax::obj &val, size_t which_dsp){
+void e100_impl::duc_set(const wax::obj &key_, const wax::obj &val, size_t which_dsp){
     named_prop_t key = named_prop_t::extract(key_);
 
     switch(key.as<dsp_prop_t>()){
 
     case DSP_PROP_FREQ_SHIFT:{
             double new_freq = val.as<double>();
-            _iface->poke32(UE_REG_DSP_TX_FREQ,
+            _iface->poke32(E100_REG_DSP_TX_FREQ,
                 dsp_type1::calc_cordic_word_and_update(new_freq, _clock_ctrl->get_fpga_clock_rate())
             );
             _dsp_impl->duc_freq[which_dsp] = new_freq; //shadow
@@ -204,10 +204,10 @@ void usrp_e100_impl::duc_set(const wax::obj &key_, const wax::obj &val, size_t w
             _dsp_impl->duc_interp[which_dsp] = boost::math::iround(_clock_ctrl->get_fpga_clock_rate()/val.as<double>());
 
             //set the interpolation
-            _iface->poke32(UE_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_dsp_impl->duc_interp[which_dsp]));
+            _iface->poke32(E100_REG_DSP_TX_INTERP_RATE, dsp_type1::calc_cic_filter_word(_dsp_impl->duc_interp[which_dsp]));
 
             //set the scaling
-            _iface->poke32(UE_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_dsp_impl->duc_interp[which_dsp]));
+            _iface->poke32(E100_REG_DSP_TX_SCALE_IQ, dsp_type1::calc_iq_scale_word(_dsp_impl->duc_interp[which_dsp]));
         }
         this->update_xport_channel_mapping(); //rate changed -> update
         return;
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp b/host/lib/usrp/e100/e100_iface.cpp
index 93c8cc7b5..d61ef42ad 100644
--- a/host/lib/usrp/usrp_e100/usrp_e100_iface.cpp
+++ b/host/lib/usrp/e100/e100_iface.cpp
@@ -15,8 +15,8 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-#include "usrp_e100_iface.hpp"
-#include "usrp_e100_regs.hpp"
+#include "e100_iface.hpp"
+#include "e100_regs.hpp"
 #include <uhd/exception.hpp>
 #include <uhd/utils/msg.hpp>
 #include <sys/ioctl.h> //ioctl
@@ -94,7 +94,7 @@ private: int _node_fd;
 /***********************************************************************
  * USRP-E100 interface implementation
  **********************************************************************/
-class usrp_e100_iface_impl : public usrp_e100_iface{
+class e100_iface_impl : public e100_iface{
 public:
 
     int get_file_descriptor(void){
@@ -127,14 +127,14 @@ public:
     /*******************************************************************
      * Structors
      ******************************************************************/
-    usrp_e100_iface_impl(void):
+    e100_iface_impl(void):
         _node_fd(-1),
         _i2c_dev_iface(i2c_dev_iface("/dev/i2c-3"))
     {
         mb_eeprom = mboard_eeprom_t(get_i2c_dev_iface(), mboard_eeprom_t::MAP_E100);
     }
 
-    ~usrp_e100_iface_impl(void){
+    ~e100_iface_impl(void){
         if (_node_fd >= 0) this->close();
     }
 
@@ -388,6 +388,6 @@ private:
 /***********************************************************************
  * Public Make Function
  **********************************************************************/
-usrp_e100_iface::sptr usrp_e100_iface::make(void){
-    return sptr(new usrp_e100_iface_impl());
+e100_iface::sptr e100_iface::make(void){
+    return sptr(new e100_iface_impl());
 }
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_iface.hpp b/host/lib/usrp/e100/e100_iface.hpp
index c7fa13393..a0135a468 100644
--- a/host/lib/usrp/usrp_e100/usrp_e100_iface.hpp
+++ b/host/lib/usrp/e100/e100_iface.hpp
@@ -15,8 +15,8 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-#ifndef INCLUDED_USRP_E100_IFACE_HPP
-#define INCLUDED_USRP_E100_IFACE_HPP
+#ifndef INCLUDED_E100_IFACE_HPP
+#define INCLUDED_E100_IFACE_HPP
 
 #include <uhd/transport/udp_simple.hpp>
 #include <uhd/usrp/mboard_eeprom.hpp>
@@ -40,9 +40,9 @@
  * Provides a set of functions to implementation layer.
  * Including spi, peek, poke, control...
  */
-class usrp_e100_iface : boost::noncopyable, public uhd::usrp::mboard_iface{
+class e100_iface : boost::noncopyable, public uhd::usrp::mboard_iface{
 public:
-    typedef boost::shared_ptr<usrp_e100_iface> sptr;
+    typedef boost::shared_ptr<e100_iface> sptr;
 
     /*!
      * Make a new usrp-e interface with the control transport.
@@ -87,4 +87,4 @@ public:
     uhd::usrp::mboard_eeprom_t mb_eeprom;
 };
 
-#endif /* INCLUDED_USRP_E100_IFACE_HPP */
+#endif /* INCLUDED_E100_IFACE_HPP */
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp b/host/lib/usrp/e100/e100_impl.cpp
index c55d80a34..5485388f9 100644
--- a/host/lib/usrp/usrp_e100/usrp_e100_impl.cpp
+++ b/host/lib/usrp/e100/e100_impl.cpp
@@ -15,8 +15,8 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-#include "usrp_e100_impl.hpp"
-#include "usrp_e100_regs.hpp"
+#include "e100_impl.hpp"
+#include "e100_regs.hpp"
 #include <uhd/utils/msg.hpp>
 #include <uhd/usrp/device_props.hpp>
 #include <uhd/usrp/mboard_props.hpp>
@@ -35,17 +35,17 @@ namespace fs = boost::filesystem;
 /***********************************************************************
  * Discovery
  **********************************************************************/
-static device_addrs_t usrp_e100_find(const device_addr_t &hint){
-    device_addrs_t usrp_e100_addrs;
+static device_addrs_t e100_find(const device_addr_t &hint){
+    device_addrs_t e100_addrs;
 
     //return an empty list of addresses when type is set to non-usrp-e
-    if (hint.has_key("type") and hint["type"] != "e100") return usrp_e100_addrs;
+    if (hint.has_key("type") and hint["type"] != "e100") return e100_addrs;
 
     //device node not provided, assume its 0
     if (not hint.has_key("node")){
         device_addr_t new_addr = hint;
         new_addr["node"] = "/dev/usrp_e0";
-        return usrp_e100_find(new_addr);
+        return e100_find(new_addr);
     }
 
     //use the given device node name
@@ -54,7 +54,7 @@ static device_addrs_t usrp_e100_find(const device_addr_t &hint){
         new_addr["type"] = "e100";
         new_addr["node"] = fs::system_complete(fs::path(hint["node"])).string();
         try{
-            usrp_e100_iface::sptr iface = usrp_e100_iface::make();
+            e100_iface::sptr iface = e100_iface::make();
             new_addr["name"] = iface->mb_eeprom["name"];
             new_addr["serial"] = iface->mb_eeprom["serial"];
         }
@@ -66,11 +66,11 @@ static device_addrs_t usrp_e100_find(const device_addr_t &hint){
             (not hint.has_key("name")   or hint["name"]   == new_addr["name"]) and
             (not hint.has_key("serial") or hint["serial"] == new_addr["serial"])
         ){
-            usrp_e100_addrs.push_back(new_addr);
+            e100_addrs.push_back(new_addr);
         }
     }
 
-    return usrp_e100_addrs;
+    return e100_addrs;
 }
 
 /***********************************************************************
@@ -85,28 +85,28 @@ static size_t hash_fpga_file(const std::string &file_path){
     return hash;
 }
 
-static device::sptr usrp_e100_make(const device_addr_t &device_addr){
+static device::sptr e100_make(const device_addr_t &device_addr){
 
     //setup the main interface into fpga
     const std::string node = device_addr["node"];
-    usrp_e100_iface::sptr iface = usrp_e100_iface::make();
+    e100_iface::sptr iface = e100_iface::make();
     iface->open(node);
 
     //setup clock control here to ensure that the FPGA has a good clock before we continue
     const double master_clock_rate = device_addr.cast<double>("master_clock_rate", E100_DEFAULT_CLOCK_RATE);
-    usrp_e100_clock_ctrl::sptr clock_ctrl = usrp_e100_clock_ctrl::make(iface, master_clock_rate);
+    e100_clock_ctrl::sptr clock_ctrl = e100_clock_ctrl::make(iface, master_clock_rate);
 
     //extract the fpga path for usrp-e and compute hash
-    const std::string usrp_e100_fpga_image = find_image_path(device_addr.get("fpga", E100_FPGA_FILE_NAME));
-    const boost::uint32_t file_hash = boost::uint32_t(hash_fpga_file(usrp_e100_fpga_image));
+    const std::string e100_fpga_image = find_image_path(device_addr.get("fpga", E100_FPGA_FILE_NAME));
+    const boost::uint32_t file_hash = boost::uint32_t(hash_fpga_file(e100_fpga_image));
 
     //When the hash does not match:
     // - close the device node
     // - load the fpga bin file
     // - re-open the device node
-    if (iface->peek32(UE_REG_RB_MISC_TEST32) != file_hash){
+    if (iface->peek32(E100_REG_RB_MISC_TEST32) != file_hash){
         iface->close();
-        usrp_e100_load_fpga(usrp_e100_fpga_image);
+        e100_load_fpga(e100_fpga_image);
         iface->open(node);
     }
 
@@ -114,8 +114,8 @@ static device::sptr usrp_e100_make(const device_addr_t &device_addr){
     bool test_fail = false;
     UHD_MSG(status) << "Performing wishbone readback test... " << std::flush;
     for (size_t i = 0; i < 100; i++){
-        iface->poke32(UE_REG_SR_MISC_TEST32, file_hash);
-        test_fail = iface->peek32(UE_REG_RB_MISC_TEST32) != file_hash;
+        iface->poke32(E100_REG_SR_MISC_TEST32, file_hash);
+        test_fail = iface->peek32(E100_REG_RB_MISC_TEST32) != file_hash;
         if (test_fail) break; //exit loop on any failure
     }
     UHD_MSG(status) << ((test_fail)? " fail" : "pass") << std::endl;
@@ -127,7 +127,7 @@ static device::sptr usrp_e100_make(const device_addr_t &device_addr){
     );
 
     //check that the compatibility is correct
-    const boost::uint16_t fpga_compat_num = iface->peek16(UE_REG_MISC_COMPAT);
+    const boost::uint16_t fpga_compat_num = iface->peek16(E100_REG_MISC_COMPAT);
     if (fpga_compat_num != E100_FPGA_COMPAT_NUM){
         throw uhd::runtime_error(str(boost::format(
             "\nPlease update the FPGA image for your device.\n"
@@ -137,25 +137,25 @@ static device::sptr usrp_e100_make(const device_addr_t &device_addr){
         ) % E100_FPGA_COMPAT_NUM % fpga_compat_num));
     }
 
-    return device::sptr(new usrp_e100_impl(device_addr, iface, clock_ctrl));
+    return device::sptr(new e100_impl(device_addr, iface, clock_ctrl));
 }
 
-UHD_STATIC_BLOCK(register_usrp_e100_device){
-    device::register_device(&usrp_e100_find, &usrp_e100_make);
+UHD_STATIC_BLOCK(register_e100_device){
+    device::register_device(&e100_find, &e100_make);
 }
 
 /***********************************************************************
  * Structors
  **********************************************************************/
-usrp_e100_impl::usrp_e100_impl(
+e100_impl::e100_impl(
     const uhd::device_addr_t &device_addr,
-    usrp_e100_iface::sptr iface,
-    usrp_e100_clock_ctrl::sptr clock_ctrl
+    e100_iface::sptr iface,
+    e100_clock_ctrl::sptr clock_ctrl
 ):
     _iface(iface),
     _clock_ctrl(clock_ctrl),
-    _codec_ctrl(usrp_e100_codec_ctrl::make(_iface)),
-    _data_xport(usrp_e100_make_mmap_zero_copy(_iface)),
+    _codec_ctrl(e100_codec_ctrl::make(_iface)),
+    _data_xport(e100_make_mmap_zero_copy(_iface)),
     _recv_frame_size(std::min(_data_xport->get_recv_frame_size(), size_t(device_addr.cast<double>("recv_frame_size", 1e9)))),
     _send_frame_size(std::min(_data_xport->get_send_frame_size(), size_t(device_addr.cast<double>("send_frame_size", 1e9))))
 {
@@ -190,14 +190,14 @@ usrp_e100_impl::usrp_e100_impl(
 
 }
 
-usrp_e100_impl::~usrp_e100_impl(void){
+e100_impl::~e100_impl(void){
     /* NOP */
 }
 
 /***********************************************************************
  * Device Get
  **********************************************************************/
-void usrp_e100_impl::get(const wax::obj &key_, wax::obj &val){
+void e100_impl::get(const wax::obj &key_, wax::obj &val){
     named_prop_t key = named_prop_t::extract(key_);
 
     //handle the get request conditioned on the key
@@ -222,6 +222,6 @@ void usrp_e100_impl::get(const wax::obj &key_, wax::obj &val){
 /***********************************************************************
  * Device Set
  **********************************************************************/
-void usrp_e100_impl::set(const wax::obj &, const wax::obj &){
+void e100_impl::set(const wax::obj &, const wax::obj &){
     UHD_THROW_PROP_SET_ERROR();
 }
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp b/host/lib/usrp/e100/e100_impl.hpp
index 4aad18fab..1390559a0 100644
--- a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp
+++ b/host/lib/usrp/e100/e100_impl.hpp
@@ -15,7 +15,7 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-#include "usrp_e100_iface.hpp"
+#include "e100_iface.hpp"
 #include "clock_ctrl.hpp"
 #include "codec_ctrl.hpp"
 #include <uhd/device.hpp>
@@ -28,10 +28,10 @@
 #include <uhd/usrp/dboard_manager.hpp>
 #include <uhd/transport/zero_copy.hpp>
 
-#ifndef INCLUDED_USRP_E100_IMPL_HPP
-#define INCLUDED_USRP_E100_IMPL_HPP
+#ifndef INCLUDED_E100_IMPL_HPP
+#define INCLUDED_E100_IMPL_HPP
 
-uhd::transport::zero_copy_if::sptr usrp_e100_make_mmap_zero_copy(usrp_e100_iface::sptr iface);
+uhd::transport::zero_copy_if::sptr e100_make_mmap_zero_copy(e100_iface::sptr iface);
 
 static const std::string     E100_FPGA_FILE_NAME = "usrp_e100_fpga5.bin";
 static const boost::uint16_t E100_FPGA_COMPAT_NUM = 0x05;
@@ -42,7 +42,7 @@ static const boost::uint32_t E100_DSP_SID_BASE = 2; //leave room for other dsp (
 static const boost::uint32_t E100_ASYNC_SID = 1;
 
 //! load an fpga image from a bin file into the usrp-e fpga
-extern void usrp_e100_load_fpga(const std::string &bin_file);
+extern void e100_load_fpga(const std::string &bin_file);
 
 /*!
  * Make a usrp-e dboard interface.
@@ -52,9 +52,9 @@ extern void usrp_e100_load_fpga(const std::string &bin_file);
  * \return a sptr to a new dboard interface
  */
 uhd::usrp::dboard_iface::sptr make_usrp_e100_dboard_iface(
-    usrp_e100_iface::sptr iface,
-    usrp_e100_clock_ctrl::sptr clock,
-    usrp_e100_codec_ctrl::sptr codec
+    e100_iface::sptr iface,
+    e100_clock_ctrl::sptr clock,
+    e100_codec_ctrl::sptr codec
 );
 
 /*!
@@ -85,15 +85,15 @@ private:
  * The implementation details are encapsulated here.
  * Handles properties on the mboard, dboard, dsps...
  */
-class usrp_e100_impl : public uhd::device{
+class e100_impl : public uhd::device{
 public:
     //structors
-    usrp_e100_impl(
+    e100_impl(
         const uhd::device_addr_t &,
-        usrp_e100_iface::sptr,
-        usrp_e100_clock_ctrl::sptr
+        e100_iface::sptr,
+        e100_clock_ctrl::sptr
     );
-    ~usrp_e100_impl(void);
+    ~e100_impl(void);
 
     //the io interface
     size_t send(const send_buffs_type &, size_t, const uhd::tx_metadata_t &, const uhd::io_type_t &, send_mode_t, double);
@@ -104,13 +104,13 @@ public:
 
 private:
     //interface to ioctls and file descriptor
-    usrp_e100_iface::sptr _iface;
+    e100_iface::sptr _iface;
 
     //ad9522 clock control
-    usrp_e100_clock_ctrl::sptr _clock_ctrl;
+    e100_clock_ctrl::sptr _clock_ctrl;
 
     //ad9862 codec control
-    usrp_e100_codec_ctrl::sptr _codec_ctrl;
+    e100_codec_ctrl::sptr _codec_ctrl;
 
     //handle io stuff
     uhd::transport::zero_copy_if::sptr _data_xport;
@@ -180,4 +180,4 @@ private:
     void update_clock_config(void);
 };
 
-#endif /* INCLUDED_USRP_E100_IMPL_HPP */
+#endif /* INCLUDED_E100_IMPL_HPP */
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_mmap_zero_copy.cpp b/host/lib/usrp/e100/e100_mmap_zero_copy.cpp
index bb421507a..5370b7594 100644
--- a/host/lib/usrp/usrp_e100/usrp_e100_mmap_zero_copy.cpp
+++ b/host/lib/usrp/e100/e100_mmap_zero_copy.cpp
@@ -15,7 +15,7 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-#include "usrp_e100_iface.hpp"
+#include "e100_iface.hpp"
 #include <uhd/transport/zero_copy.hpp>
 #include <uhd/utils/log.hpp>
 #include <uhd/exception.hpp>
@@ -35,9 +35,9 @@ static const size_t poll_breakout = 10; //how many poll timeouts constitute a fu
  * Reusable managed receiver buffer:
  *  - The buffer knows how to claim and release a frame.
  **********************************************************************/
-class usrp_e100_mmap_zero_copy_mrb : public managed_recv_buffer{
+class e100_mmap_zero_copy_mrb : public managed_recv_buffer{
 public:
-    usrp_e100_mmap_zero_copy_mrb(void *mem, ring_buffer_info *info):
+    e100_mmap_zero_copy_mrb(void *mem, ring_buffer_info *info):
         _mem(mem), _info(info) { /* NOP */ }
 
     void release(void){
@@ -66,9 +66,9 @@ private:
  * Reusable managed send buffer:
  *  - The buffer knows how to claim and release a frame.
  **********************************************************************/
-class usrp_e100_mmap_zero_copy_msb : public managed_send_buffer{
+class e100_mmap_zero_copy_msb : public managed_send_buffer{
 public:
-    usrp_e100_mmap_zero_copy_msb(void *mem, ring_buffer_info *info, size_t len, int fd):
+    e100_mmap_zero_copy_msb(void *mem, ring_buffer_info *info, size_t len, int fd):
         _mem(mem), _info(info), _len(len), _fd(fd) { /* NOP */ }
 
     void commit(size_t len){
@@ -102,9 +102,9 @@ private:
 /***********************************************************************
  * The zero copy interface implementation
  **********************************************************************/
-class usrp_e100_mmap_zero_copy_impl : public zero_copy_if{
+class e100_mmap_zero_copy_impl : public zero_copy_if{
 public:
-    usrp_e100_mmap_zero_copy_impl(usrp_e100_iface::sptr iface):
+    e100_mmap_zero_copy_impl(e100_iface::sptr iface):
         _fd(iface->get_file_descriptor()), _recv_index(0), _send_index(0)
     {
         //get system sizes
@@ -162,28 +162,28 @@ public:
 
         //initialize the managed receive buffers
         for (size_t i = 0; i < get_num_recv_frames(); i++){
-            _mrb_pool.push_back(usrp_e100_mmap_zero_copy_mrb(
+            _mrb_pool.push_back(e100_mmap_zero_copy_mrb(
                 recv_buff + get_recv_frame_size()*i, (*recv_info) + i
             ));
         }
 
         //initialize the managed send buffers
         for (size_t i = 0; i < get_num_recv_frames(); i++){
-            _msb_pool.push_back(usrp_e100_mmap_zero_copy_msb(
+            _msb_pool.push_back(e100_mmap_zero_copy_msb(
                 send_buff + get_send_frame_size()*i, (*send_info) + i,
                 get_send_frame_size(), _fd
             ));
         }
     }
 
-    ~usrp_e100_mmap_zero_copy_impl(void){
+    ~e100_mmap_zero_copy_impl(void){
         UHD_LOG << "cleanup: munmap" << std::endl;
         ::munmap(_mapped_mem, _map_size);
     }
 
     managed_recv_buffer::sptr get_recv_buff(double timeout){
         if (fp_verbose) UHD_LOGV(always) << "get_recv_buff: " << _recv_index << std::endl;
-        usrp_e100_mmap_zero_copy_mrb &mrb = _mrb_pool[_recv_index];
+        e100_mmap_zero_copy_mrb &mrb = _mrb_pool[_recv_index];
 
         //poll/wait for a ready frame
         if (not mrb.ready()){
@@ -215,7 +215,7 @@ public:
 
     managed_send_buffer::sptr get_send_buff(double timeout){
         if (fp_verbose) UHD_LOGV(always) << "get_send_buff: " << _send_index << std::endl;
-        usrp_e100_mmap_zero_copy_msb &msb = _msb_pool[_send_index];
+        e100_mmap_zero_copy_msb &msb = _msb_pool[_send_index];
 
         //poll/wait for a ready frame
         if (not msb.ready()){
@@ -254,8 +254,8 @@ private:
     size_t _frame_size, _map_size;
 
     //re-usable managed buffers
-    std::vector<usrp_e100_mmap_zero_copy_mrb> _mrb_pool;
-    std::vector<usrp_e100_mmap_zero_copy_msb> _msb_pool;
+    std::vector<e100_mmap_zero_copy_mrb> _mrb_pool;
+    std::vector<e100_mmap_zero_copy_msb> _msb_pool;
 
     //indexes into sub-sections of mapped memory
     size_t _recv_index, _send_index;
@@ -264,6 +264,6 @@ private:
 /***********************************************************************
  * The zero copy interface make function
  **********************************************************************/
-zero_copy_if::sptr usrp_e100_make_mmap_zero_copy(usrp_e100_iface::sptr iface){
-    return zero_copy_if::sptr(new usrp_e100_mmap_zero_copy_impl(iface));
+zero_copy_if::sptr e100_make_mmap_zero_copy(e100_iface::sptr iface){
+    return zero_copy_if::sptr(new e100_mmap_zero_copy_impl(iface));
 }
diff --git a/host/lib/usrp/e100/e100_regs.hpp b/host/lib/usrp/e100/e100_regs.hpp
new file mode 100644
index 000000000..5be607389
--- /dev/null
+++ b/host/lib/usrp/e100/e100_regs.hpp
@@ -0,0 +1,242 @@
+
+
+////////////////////////////////////////////////////////////////
+//
+//         Memory map for embedded wishbone bus
+//
+////////////////////////////////////////////////////////////////
+
+// All addresses are byte addresses.  All accesses are word (16-bit) accesses.
+//  This means that address bit 0 is usually 0.
+//  There are 11 bits of address for the control.
+
+#ifndef INCLUDED_E100_REGS_HPP
+#define INCLUDED_E100_REGS_HPP
+
+/////////////////////////////////////////////////////
+// Slave pointers
+
+#define E100_REG_SLAVE(n) ((n)<<7)
+
+/////////////////////////////////////////////////////
+// Slave 0 -- Misc Regs
+
+#define E100_REG_MISC_BASE E100_REG_SLAVE(0)
+
+#define E100_REG_MISC_LED        E100_REG_MISC_BASE + 0
+#define E100_REG_MISC_SW         E100_REG_MISC_BASE + 2
+#define E100_REG_MISC_CGEN_CTRL  E100_REG_MISC_BASE + 4
+#define E100_REG_MISC_CGEN_ST    E100_REG_MISC_BASE + 6
+#define E100_REG_MISC_TEST       E100_REG_MISC_BASE + 8
+#define E100_REG_MISC_RX_LEN     E100_REG_MISC_BASE + 10
+#define E100_REG_MISC_TX_LEN     E100_REG_MISC_BASE + 12
+#define E100_REG_MISC_XFER_RATE  E100_REG_MISC_BASE + 14
+#define E100_REG_MISC_COMPAT     E100_REG_MISC_BASE + 16
+
+/////////////////////////////////////////////////////
+// Slave 1 -- UART
+//   CLKDIV is 16 bits, others are only 8
+
+#define E100_REG_UART_BASE E100_REG_SLAVE(1)
+
+#define E100_REG_UART_CLKDIV  E100_REG_UART_BASE + 0
+#define E100_REG_UART_TXLEVEL E100_REG_UART_BASE + 2
+#define E100_REG_UART_RXLEVEL E100_REG_UART_BASE + 4
+#define E100_REG_UART_TXCHAR  E100_REG_UART_BASE + 6
+#define E100_REG_UART_RXCHAR  E100_REG_UART_BASE + 8
+
+/////////////////////////////////////////////////////
+// Slave 2 -- SPI Core
+//   This should be accessed through the IOCTL
+//   Users should not touch directly
+
+#define E100_REG_SPI_BASE E100_REG_SLAVE(2)
+
+//spi slave constants
+#define UE_SPI_SS_AD9522    (1 << 3)
+#define UE_SPI_SS_AD9862    (1 << 2)
+#define UE_SPI_SS_TX_DB     (1 << 1)
+#define UE_SPI_SS_RX_DB     (1 << 0)
+
+////////////////////////////////////////////////
+// Slave 3 -- I2C Core
+//   This should be accessed through the IOCTL
+//   Users should not touch directly
+
+#define E100_REG_I2C_BASE E100_REG_SLAVE(3)
+
+
+////////////////////////////////////////////////
+// Slave 4 -- GPIO
+
+#define E100_REG_GPIO_BASE E100_REG_SLAVE(4)
+
+#define E100_REG_GPIO_RX_IO      E100_REG_GPIO_BASE + 0
+#define E100_REG_GPIO_TX_IO      E100_REG_GPIO_BASE + 2
+#define E100_REG_GPIO_RX_DDR     E100_REG_GPIO_BASE + 4
+#define E100_REG_GPIO_TX_DDR     E100_REG_GPIO_BASE + 6
+#define E100_REG_GPIO_RX_SEL     E100_REG_GPIO_BASE + 8
+#define E100_REG_GPIO_TX_SEL     E100_REG_GPIO_BASE + 10
+#define E100_REG_GPIO_RX_DBG     E100_REG_GPIO_BASE + 12
+#define E100_REG_GPIO_TX_DBG     E100_REG_GPIO_BASE + 14
+
+//possible bit values for sel when dbg is 0:
+#define GPIO_SEL_SW    0 // if pin is an output, set by software in the io reg
+#define GPIO_SEL_ATR   1 // if pin is an output, set by ATR logic
+
+//possible bit values for sel when dbg is 1:
+#define GPIO_SEL_DEBUG_0   0 // if pin is an output, debug lines from FPGA fabric
+#define GPIO_SEL_DEBUG_1   1 // if pin is an output, debug lines from FPGA fabric
+
+///////////////////////////////////////////////////
+// Slave 6 -- ATR Controller
+//   16 regs
+
+#define E100_REG_ATR_BASE  E100_REG_SLAVE(6)
+
+#define	E100_REG_ATR_IDLE_RXSIDE  E100_REG_ATR_BASE + 0
+#define	E100_REG_ATR_IDLE_TXSIDE  E100_REG_ATR_BASE + 2
+#define E100_REG_ATR_INTX_RXSIDE  E100_REG_ATR_BASE + 4
+#define E100_REG_ATR_INTX_TXSIDE  E100_REG_ATR_BASE + 6
+#define	E100_REG_ATR_INRX_RXSIDE  E100_REG_ATR_BASE + 8
+#define	E100_REG_ATR_INRX_TXSIDE  E100_REG_ATR_BASE + 10
+#define	E100_REG_ATR_FULL_RXSIDE  E100_REG_ATR_BASE + 12
+#define	E100_REG_ATR_FULL_TXSIDE  E100_REG_ATR_BASE + 14
+
+///////////////////////////////////////////////////
+// Slave 7 -- Readback Mux 32
+
+#define E100_REG_RB_MUX_32_BASE  E100_REG_SLAVE(7)
+
+#define E100_REG_RB_TIME_NOW_SECS   E100_REG_RB_MUX_32_BASE + 0
+#define E100_REG_RB_TIME_NOW_TICKS  E100_REG_RB_MUX_32_BASE + 4
+#define E100_REG_RB_TIME_PPS_SECS   E100_REG_RB_MUX_32_BASE + 8
+#define E100_REG_RB_TIME_PPS_TICKS  E100_REG_RB_MUX_32_BASE + 12
+#define E100_REG_RB_MISC_TEST32     E100_REG_RB_MUX_32_BASE + 16
+
+////////////////////////////////////////////////////
+// Slave 8 -- Settings Bus
+//
+// Output-only, no readback, 64 registers total
+//  Each register must be written 64 bits at a time
+//  First the address xxx_xx00 and then xxx_xx10
+
+// 64 total regs in address space
+#define UE_SR_RX_CTRL0 0       // 9 regs (+0 to +8)
+#define UE_SR_RX_DSP0 10       // 4 regs (+0 to +3)
+#define UE_SR_RX_CTRL1 16      // 9 regs (+0 to +8)
+#define UE_SR_RX_DSP1 26       // 4 regs (+0 to +3)
+#define UE_SR_TX_CTRL 32       // 4 regs (+0 to +3)
+#define UE_SR_TX_DSP 38        // 3 regs (+0 to +2)
+
+#define UE_SR_TIME64 42        // 6 regs (+0 to +5)
+#define UE_SR_RX_FRONT 48      // 5 regs (+0 to +4)
+#define UE_SR_TX_FRONT 54      // 5 regs (+0 to +4)
+
+#define UE_SR_REG_TEST32 60    // 1 reg
+#define UE_SR_CLEAR_RX_FIFO 61 // 1 reg
+#define UE_SR_CLEAR_TX_FIFO 62 // 1 reg
+#define UE_SR_GLOBAL_RESET 63  // 1 reg
+
+#define E100_REG_SR_ADDR(n) (E100_REG_SLAVE(8) + (4*(n)))
+
+#define E100_REG_SR_MISC_TEST32        E100_REG_SR_ADDR(UE_SR_REG_TEST32)
+
+/////////////////////////////////////////////////
+// Magic reset regs
+////////////////////////////////////////////////
+#define E100_REG_CLEAR_RX           E100_REG_SR_ADDR(UE_SR_CLEAR_RX_FIFO)
+#define E100_REG_CLEAR_TX           E100_REG_SR_ADDR(UE_SR_CLEAR_RX_FIFO)
+#define E100_REG_GLOBAL_RESET       E100_REG_SR_ADDR(UE_SR_GLOBAL_RESET)
+
+/////////////////////////////////////////////////
+// DSP RX Regs
+////////////////////////////////////////////////
+#define E100_REG_DSP_RX_HELPER(which, offset) ((which == 0)? \
+    (E100_REG_SR_ADDR(UE_SR_RX_DSP0 + offset)) : \
+    (E100_REG_SR_ADDR(UE_SR_RX_DSP1 + offset)))
+
+#define E100_REG_DSP_RX_FREQ(which)       E100_REG_DSP_RX_HELPER(which, 0)
+#define E100_REG_DSP_RX_DECIM(which)      E100_REG_DSP_RX_HELPER(which, 2)
+#define E100_REG_DSP_RX_MUX(which)        E100_REG_DSP_RX_HELPER(which, 3)
+
+#define E100_FLAG_DSP_RX_MUX_SWAP_IQ   (1 << 0)
+#define E100_FLAG_DSP_RX_MUX_REAL_MODE (1 << 1)
+
+///////////////////////////////////////////////////
+// RX CTRL regs
+///////////////////////////////////////////////////
+#define E100_REG_RX_CTRL_HELPER(which, offset) ((which == 0)? \
+    (E100_REG_SR_ADDR(UE_SR_RX_CTRL0 + offset)) : \
+    (E100_REG_SR_ADDR(UE_SR_RX_CTRL1 + offset)))
+
+#define E100_REG_RX_CTRL_STREAM_CMD(which)     E100_REG_RX_CTRL_HELPER(which, 0)
+#define E100_REG_RX_CTRL_TIME_SECS(which)      E100_REG_RX_CTRL_HELPER(which, 1)
+#define E100_REG_RX_CTRL_TIME_TICKS(which)     E100_REG_RX_CTRL_HELPER(which, 2)
+#define E100_REG_RX_CTRL_CLEAR(which)          E100_REG_RX_CTRL_HELPER(which, 3)
+#define E100_REG_RX_CTRL_VRT_HDR(which)        E100_REG_RX_CTRL_HELPER(which, 4)
+#define E100_REG_RX_CTRL_VRT_SID(which)        E100_REG_RX_CTRL_HELPER(which, 5)
+#define E100_REG_RX_CTRL_VRT_TLR(which)        E100_REG_RX_CTRL_HELPER(which, 6)
+#define E100_REG_RX_CTRL_NSAMPS_PP(which)      E100_REG_RX_CTRL_HELPER(which, 7)
+#define E100_REG_RX_CTRL_NCHANNELS(which)      E100_REG_RX_CTRL_HELPER(which, 8)
+
+/////////////////////////////////////////////////
+// RX FE
+////////////////////////////////////////////////
+#define E100_REG_RX_FE_SWAP_IQ             E100_REG_SR_ADDR(UE_SR_RX_FRONT + 0) //lower bit
+#define E100_REG_RX_FE_MAG_CORRECTION      E100_REG_SR_ADDR(UE_SR_RX_FRONT + 1) //18 bits
+#define E100_REG_RX_FE_PHASE_CORRECTION    E100_REG_SR_ADDR(UE_SR_RX_FRONT + 2) //18 bits
+#define E100_REG_RX_FE_OFFSET_I            E100_REG_SR_ADDR(UE_SR_RX_FRONT + 3) //18 bits
+#define E100_REG_RX_FE_OFFSET_Q            E100_REG_SR_ADDR(UE_SR_RX_FRONT + 4) //18 bits
+
+/////////////////////////////////////////////////
+// DSP TX Regs
+////////////////////////////////////////////////
+#define E100_REG_DSP_TX_FREQ          E100_REG_SR_ADDR(UE_SR_TX_DSP + 0)
+#define E100_REG_DSP_TX_SCALE_IQ      E100_REG_SR_ADDR(UE_SR_TX_DSP + 1)
+#define E100_REG_DSP_TX_INTERP_RATE   E100_REG_SR_ADDR(UE_SR_TX_DSP + 2)
+
+///////////////////////////////////////////////////
+// TX CTRL regs
+///////////////////////////////////////////////////
+#define E100_REG_TX_CTRL_NUM_CHAN       E100_REG_SR_ADDR(UE_SR_TX_CTRL + 0)
+#define E100_REG_TX_CTRL_CLEAR_STATE    E100_REG_SR_ADDR(UE_SR_TX_CTRL + 1)
+#define E100_REG_TX_CTRL_REPORT_SID     E100_REG_SR_ADDR(UE_SR_TX_CTRL + 2)
+#define E100_REG_TX_CTRL_POLICY         E100_REG_SR_ADDR(UE_SR_TX_CTRL + 3)
+#define E100_REG_TX_CTRL_CYCLES_PER_UP  E100_REG_SR_ADDR(UE_SR_TX_CTRL + 4)
+#define E100_REG_TX_CTRL_PACKETS_PER_UP E100_REG_SR_ADDR(UE_SR_TX_CTRL + 5)
+
+#define E100_FLAG_TX_CTRL_POLICY_WAIT          (0x1 << 0)
+#define E100_FLAG_TX_CTRL_POLICY_NEXT_PACKET   (0x1 << 1)
+#define E100_FLAG_TX_CTRL_POLICY_NEXT_BURST    (0x1 << 2)
+
+/////////////////////////////////////////////////
+// TX FE
+////////////////////////////////////////////////
+#define E100_REG_TX_FE_DC_OFFSET_I         E100_REG_SR_ADDR(UE_SR_TX_FRONT + 0) //24 bits
+#define E100_REG_TX_FE_DC_OFFSET_Q         E100_REG_SR_ADDR(UE_SR_TX_FRONT + 1) //24 bits
+#define E100_REG_TX_FE_MAC_CORRECTION      E100_REG_SR_ADDR(UE_SR_TX_FRONT + 2) //18 bits
+#define E100_REG_TX_FE_PHASE_CORRECTION    E100_REG_SR_ADDR(UE_SR_TX_FRONT + 3) //18 bits
+#define E100_REG_TX_FE_MUX                 E100_REG_SR_ADDR(UE_SR_TX_FRONT + 4) //8 bits (std output = 0x10, reversed = 0x01)
+
+/////////////////////////////////////////////////
+// VITA49 64 bit time (write only)
+////////////////////////////////////////////////
+#define E100_REG_TIME64_SECS      E100_REG_SR_ADDR(UE_SR_TIME64 + 0)
+#define E100_REG_TIME64_TICKS     E100_REG_SR_ADDR(UE_SR_TIME64 + 1)
+#define E100_REG_TIME64_FLAGS     E100_REG_SR_ADDR(UE_SR_TIME64 + 2)
+#define E100_REG_TIME64_IMM       E100_REG_SR_ADDR(UE_SR_TIME64 + 3)
+#define E100_REG_TIME64_TPS       E100_REG_SR_ADDR(UE_SR_TIME64 + 4)
+#define E100_REG_TIME64_MIMO_SYNC E100_REG_SR_ADDR(UE_SR_TIME64 + 5)
+
+//pps flags (see above)
+#define E100_FLAG_TIME64_PPS_NEGEDGE (0 << 0)
+#define E100_FLAG_TIME64_PPS_POSEDGE (1 << 0)
+#define E100_FLAG_TIME64_PPS_SMA     (0 << 1)
+#define E100_FLAG_TIME64_PPS_MIMO    (1 << 1)
+
+#define E100_FLAG_TIME64_LATCH_NOW 1
+#define E100_FLAG_TIME64_LATCH_NEXT_PPS 0
+
+#endif
+
diff --git a/host/lib/usrp/usrp_e100/fpga_downloader.cpp b/host/lib/usrp/e100/fpga_downloader.cpp
index b8420796f..7074c8299 100644
--- a/host/lib/usrp/usrp_e100/fpga_downloader.cpp
+++ b/host/lib/usrp/e100/fpga_downloader.cpp
@@ -245,7 +245,7 @@ static void send_file_to_fpga(const std::string &file_name, gpio &error, gpio &d
 
 }//namespace usrp_e_fpga_downloader_utility
 
-void usrp_e100_load_fpga(const std::string &bin_file){
+void e100_load_fpga(const std::string &bin_file){
 	using namespace usrp_e_fpga_downloader_utility;
 
 	gpio gpio_prog_b(PROG_B, OUT);
diff --git a/host/lib/usrp/usrp_e100/include/linux/usrp_e.h b/host/lib/usrp/e100/include/linux/usrp_e.h
index 4c6a5dd89..4c6a5dd89 100644
--- a/host/lib/usrp/usrp_e100/include/linux/usrp_e.h
+++ b/host/lib/usrp/e100/include/linux/usrp_e.h
diff --git a/host/lib/usrp/usrp_e100/io_impl.cpp b/host/lib/usrp/e100/io_impl.cpp
index f590951dc..dc0d959fa 100644
--- a/host/lib/usrp/usrp_e100/io_impl.cpp
+++ b/host/lib/usrp/e100/io_impl.cpp
@@ -17,8 +17,8 @@
 
 #include "../../transport/super_recv_packet_handler.hpp"
 #include "../../transport/super_send_packet_handler.hpp"
-#include "usrp_e100_impl.hpp"
-#include "usrp_e100_regs.hpp"
+#include "e100_impl.hpp"
+#include "e100_regs.hpp"
 #include <uhd/utils/msg.hpp>
 #include <uhd/utils/log.hpp>
 #include <uhd/usrp/dsp_utils.hpp>
@@ -36,11 +36,6 @@ using namespace uhd::usrp;
 using namespace uhd::transport;
 
 /***********************************************************************
- * Constants
- **********************************************************************/
-static const int underflow_flags = async_metadata_t::EVENT_CODE_UNDERFLOW | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET;
-
-/***********************************************************************
  * Helpers
  **********************************************************************/
 #if 1
@@ -66,7 +61,7 @@ static void debug_print_buff(const std::string &what, managed_recv_buffer::sptr
  * - thread loop
  * - vrt packet handler states
  **********************************************************************/
-struct usrp_e100_impl::io_impl{
+struct e100_impl::io_impl{
     io_impl(zero_copy_if::sptr &xport):
         data_xport(xport),
         async_msg_fifo(100/*messages deep*/)
@@ -103,7 +98,7 @@ struct usrp_e100_impl::io_impl{
     bool continuous_streaming;
 
     //a pirate's life is the life for me!
-    void recv_pirate_loop(boost::barrier &, usrp_e100_clock_ctrl::sptr);
+    void recv_pirate_loop(boost::barrier &, e100_clock_ctrl::sptr);
     std::vector<bounded_buffer<managed_recv_buffer::sptr> *> recv_pirate_booty;
     bounded_buffer<async_metadata_t> async_msg_fifo;
     boost::thread_group recv_pirate_crew;
@@ -114,8 +109,8 @@ struct usrp_e100_impl::io_impl{
  * - while raiding, loot for recv buffers
  * - put booty into the alignment buffer
  **********************************************************************/
-void usrp_e100_impl::io_impl::recv_pirate_loop(
-    boost::barrier &spawn_barrier, usrp_e100_clock_ctrl::sptr clock_ctrl
+void e100_impl::io_impl::recv_pirate_loop(
+    boost::barrier &spawn_barrier, e100_clock_ctrl::sptr clock_ctrl
 ){
     spawn_barrier.wait();
     set_thread_priority_safe();
@@ -154,10 +149,15 @@ void usrp_e100_impl::io_impl::recv_pirate_loop(
                 time_t(if_packet_info.tsi), long(if_packet_info.tsf), clock_ctrl->get_fpga_clock_rate()
             );
             metadata.event_code = async_metadata_t::event_code_t(sph::get_context_code(vrt_hdr, if_packet_info));
-
-            //print the famous U, and push the metadata into the message queue
-            if (metadata.event_code & underflow_flags) UHD_MSG(fastpath) << "U";
             async_msg_fifo.push_with_pop_on_full(metadata);
+            if (metadata.event_code &
+                ( async_metadata_t::EVENT_CODE_UNDERFLOW 
+                | async_metadata_t::EVENT_CODE_UNDERFLOW_IN_PACKET)
+            ) UHD_MSG(fastpath) << "U";
+            else if (metadata.event_code &
+                ( async_metadata_t::EVENT_CODE_SEQ_ERROR
+                | async_metadata_t::EVENT_CODE_SEQ_ERROR_IN_BURST)
+            ) UHD_MSG(fastpath) << "S";
             continue;
         }
 
@@ -168,19 +168,19 @@ void usrp_e100_impl::io_impl::recv_pirate_loop(
 /***********************************************************************
  * Helper Functions
  **********************************************************************/
-void usrp_e100_impl::io_init(void){
+void e100_impl::io_init(void){
 
     //setup before the registers (transport called to calculate max spp)
     _io_impl = UHD_PIMPL_MAKE(io_impl, (_data_xport));
 
     //clear state machines
-    _iface->poke32(UE_REG_CLEAR_RX, 0);
-    _iface->poke32(UE_REG_CLEAR_TX, 0);
+    _iface->poke32(E100_REG_CLEAR_RX, 0);
+    _iface->poke32(E100_REG_CLEAR_TX, 0);
 
     //spawn a pirate, yarrr!
     boost::barrier spawn_barrier(2);
     _io_impl->recv_pirate_crew.create_thread(boost::bind(
-        &usrp_e100_impl::io_impl::recv_pirate_loop, _io_impl.get(),
+        &e100_impl::io_impl::recv_pirate_loop, _io_impl.get(),
         boost::ref(spawn_barrier), _clock_ctrl
     ));
     spawn_barrier.wait();
@@ -188,7 +188,7 @@ void usrp_e100_impl::io_init(void){
     update_xport_channel_mapping();
 }
 
-void usrp_e100_impl::update_xport_channel_mapping(void){
+void e100_impl::update_xport_channel_mapping(void){
     if (_io_impl.get() == NULL) return; //not inited yet
 
     //set all of the relevant properties on the handler
@@ -200,10 +200,10 @@ void usrp_e100_impl::update_xport_channel_mapping(void){
     _io_impl->recv_handler.set_samp_rate(_rx_dsp_proxies[_rx_dsp_proxies.keys().at(0)]->get_link()[DSP_PROP_HOST_RATE].as<double>());
     for (size_t chan = 0; chan < _io_impl->recv_handler.size(); chan++){
         _io_impl->recv_handler.set_xport_chan_get_buff(chan, boost::bind(
-            &usrp_e100_impl::io_impl::get_recv_buff, _io_impl.get(), chan, _1
+            &e100_impl::io_impl::get_recv_buff, _io_impl.get(), chan, _1
         ));
         _io_impl->recv_handler.set_overflow_handler(chan, boost::bind(
-            &usrp_e100_impl::handle_overrun, this, chan
+            &e100_impl::handle_overrun, this, chan
         ));
     }
     _io_impl->recv_handler.set_converter(_recv_otw_type);
@@ -224,14 +224,14 @@ void usrp_e100_impl::update_xport_channel_mapping(void){
     _io_impl->send_handler.set_max_samples_per_packet(get_max_send_samps_per_packet());
 }
 
-void usrp_e100_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd, const size_t index){
+void e100_impl::issue_ddc_stream_cmd(const stream_cmd_t &stream_cmd, const size_t index){
     _io_impl->continuous_streaming = (stream_cmd.stream_mode == stream_cmd_t::STREAM_MODE_START_CONTINUOUS);
-    _iface->poke32(UE_REG_RX_CTRL_STREAM_CMD(index), dsp_type1::calc_stream_cmd_word(stream_cmd));
-    _iface->poke32(UE_REG_RX_CTRL_TIME_SECS(index),  boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
-    _iface->poke32(UE_REG_RX_CTRL_TIME_TICKS(index), stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate()));
+    _iface->poke32(E100_REG_RX_CTRL_STREAM_CMD(index), dsp_type1::calc_stream_cmd_word(stream_cmd));
+    _iface->poke32(E100_REG_RX_CTRL_TIME_SECS(index),  boost::uint32_t(stream_cmd.time_spec.get_full_secs()));
+    _iface->poke32(E100_REG_RX_CTRL_TIME_TICKS(index), stream_cmd.time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate()));
 }
 
-void usrp_e100_impl::handle_overrun(const size_t index){
+void e100_impl::handle_overrun(const size_t index){
     if (_io_impl->continuous_streaming){
         this->issue_ddc_stream_cmd(stream_cmd_t::STREAM_MODE_START_CONTINUOUS, index);
     }
@@ -240,7 +240,7 @@ void usrp_e100_impl::handle_overrun(const size_t index){
 /***********************************************************************
  * Data Send
  **********************************************************************/
-size_t usrp_e100_impl::get_max_send_samps_per_packet(void) const{
+size_t e100_impl::get_max_send_samps_per_packet(void) const{
     static const size_t hdr_size = 0
         + vrt::max_if_hdr_words32*sizeof(boost::uint32_t)
         - sizeof(vrt::if_packet_info_t().cid) //no class id ever used
@@ -249,7 +249,7 @@ size_t usrp_e100_impl::get_max_send_samps_per_packet(void) const{
     return bpp/_send_otw_type.get_sample_size();
 }
 
-size_t usrp_e100_impl::send(
+size_t e100_impl::send(
     const send_buffs_type &buffs, size_t nsamps_per_buff,
     const tx_metadata_t &metadata, const io_type_t &io_type,
     send_mode_t send_mode, double timeout
@@ -264,7 +264,7 @@ size_t usrp_e100_impl::send(
 /***********************************************************************
  * Data Recv
  **********************************************************************/
-size_t usrp_e100_impl::get_max_recv_samps_per_packet(void) const{
+size_t e100_impl::get_max_recv_samps_per_packet(void) const{
     static const size_t hdr_size = 0
         + vrt::max_if_hdr_words32*sizeof(boost::uint32_t)
         + sizeof(vrt::if_packet_info_t().tlr) //forced to have trailer
@@ -274,7 +274,7 @@ size_t usrp_e100_impl::get_max_recv_samps_per_packet(void) const{
     return bpp/_recv_otw_type.get_sample_size();
 }
 
-size_t usrp_e100_impl::recv(
+size_t e100_impl::recv(
     const recv_buffs_type &buffs, size_t nsamps_per_buff,
     rx_metadata_t &metadata, const io_type_t &io_type,
     recv_mode_t recv_mode, double timeout
@@ -289,7 +289,7 @@ size_t usrp_e100_impl::recv(
 /***********************************************************************
  * Async Recv
  **********************************************************************/
-bool usrp_e100_impl::recv_async_msg(
+bool e100_impl::recv_async_msg(
     async_metadata_t &async_metadata, double timeout
 ){
     boost::this_thread::disable_interruption di; //disable because the wait can throw
diff --git a/host/lib/usrp/usrp_e100/mboard_impl.cpp b/host/lib/usrp/e100/mboard_impl.cpp
index 549c9bf4f..e7a46fe8e 100644
--- a/host/lib/usrp/usrp_e100/mboard_impl.cpp
+++ b/host/lib/usrp/e100/mboard_impl.cpp
@@ -15,8 +15,8 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-#include "usrp_e100_impl.hpp"
-#include "usrp_e100_regs.hpp"
+#include "e100_impl.hpp"
+#include "e100_regs.hpp"
 #include <uhd/utils/msg.hpp>
 #include <uhd/exception.hpp>
 #include <uhd/usrp/dsp_utils.hpp>
@@ -30,10 +30,10 @@ using namespace uhd::usrp;
 /***********************************************************************
  * Mboard Initialization
  **********************************************************************/
-void usrp_e100_impl::mboard_init(void){
+void e100_impl::mboard_init(void){
     _mboard_proxy = wax_obj_proxy::make(
-        boost::bind(&usrp_e100_impl::mboard_get, this, _1, _2),
-        boost::bind(&usrp_e100_impl::mboard_set, this, _1, _2)
+        boost::bind(&e100_impl::mboard_get, this, _1, _2),
+        boost::bind(&e100_impl::mboard_set, this, _1, _2)
     );
 
     //init the clock config
@@ -41,18 +41,18 @@ void usrp_e100_impl::mboard_init(void){
     update_clock_config();
 }
 
-void usrp_e100_impl::update_clock_config(void){
+void e100_impl::update_clock_config(void){
     boost::uint32_t pps_flags = 0;
 
     //translate pps polarity enums
     switch(_clock_config.pps_polarity){
-    case clock_config_t::PPS_POS: pps_flags |= UE_FLAG_TIME64_PPS_POSEDGE; break;
-    case clock_config_t::PPS_NEG: pps_flags |= UE_FLAG_TIME64_PPS_NEGEDGE; break;
+    case clock_config_t::PPS_POS: pps_flags |= E100_FLAG_TIME64_PPS_POSEDGE; break;
+    case clock_config_t::PPS_NEG: pps_flags |= E100_FLAG_TIME64_PPS_NEGEDGE; break;
     default: throw uhd::value_error("unhandled clock configuration pps polarity");
     }
 
     //set the pps flags
-    _iface->poke32(UE_REG_TIME64_FLAGS, pps_flags);
+    _iface->poke32(E100_REG_TIME64_FLAGS, pps_flags);
 
     //clock source ref 10mhz
     switch(_clock_config.ref_source){
@@ -66,7 +66,7 @@ void usrp_e100_impl::update_clock_config(void){
 /***********************************************************************
  * Mboard Get
  **********************************************************************/
-void usrp_e100_impl::mboard_get(const wax::obj &key_, wax::obj &val){
+void e100_impl::mboard_get(const wax::obj &key_, wax::obj &val){
     named_prop_t key = named_prop_t::extract(key_);
     static const std::string dboard_name = "A";
 
@@ -131,17 +131,17 @@ void usrp_e100_impl::mboard_get(const wax::obj &key_, wax::obj &val){
         return;
 
     case MBOARD_PROP_TIME_NOW: while(true){
-        uint32_t secs = _iface->peek32(UE_REG_RB_TIME_NOW_SECS);
-        uint32_t ticks = _iface->peek32(UE_REG_RB_TIME_NOW_TICKS);
-        if (secs != _iface->peek32(UE_REG_RB_TIME_NOW_SECS)) continue;
+        uint32_t secs = _iface->peek32(E100_REG_RB_TIME_NOW_SECS);
+        uint32_t ticks = _iface->peek32(E100_REG_RB_TIME_NOW_TICKS);
+        if (secs != _iface->peek32(E100_REG_RB_TIME_NOW_SECS)) continue;
         val = time_spec_t(secs, ticks, _clock_ctrl->get_fpga_clock_rate());
         return;
     }
 
     case MBOARD_PROP_TIME_PPS: while(true){
-        uint32_t secs = _iface->peek32(UE_REG_RB_TIME_PPS_SECS);
-        uint32_t ticks = _iface->peek32(UE_REG_RB_TIME_PPS_TICKS);
-        if (secs != _iface->peek32(UE_REG_RB_TIME_PPS_SECS)) continue;
+        uint32_t secs = _iface->peek32(E100_REG_RB_TIME_PPS_SECS);
+        uint32_t ticks = _iface->peek32(E100_REG_RB_TIME_PPS_TICKS);
+        if (secs != _iface->peek32(E100_REG_RB_TIME_PPS_SECS)) continue;
         val = time_spec_t(secs, ticks, _clock_ctrl->get_fpga_clock_rate());
         return;
     }
@@ -157,17 +157,17 @@ void usrp_e100_impl::mboard_get(const wax::obj &key_, wax::obj &val){
 /***********************************************************************
  * Mboard Set
  **********************************************************************/
-void usrp_e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){
+void e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){
     //handle the get request conditioned on the key
     switch(key.as<mboard_prop_t>()){
 
     case MBOARD_PROP_TIME_NOW:
     case MBOARD_PROP_TIME_PPS:{
             time_spec_t time_spec = val.as<time_spec_t>();
-            _iface->poke32(UE_REG_TIME64_TICKS, time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate()));
+            _iface->poke32(E100_REG_TIME64_TICKS, time_spec.get_tick_count(_clock_ctrl->get_fpga_clock_rate()));
             boost::uint32_t imm_flags = (key.as<mboard_prop_t>() == MBOARD_PROP_TIME_NOW)? 1 : 0;
-            _iface->poke32(UE_REG_TIME64_IMM, imm_flags);
-            _iface->poke32(UE_REG_TIME64_SECS, time_spec.get_full_secs());
+            _iface->poke32(E100_REG_TIME64_IMM, imm_flags);
+            _iface->poke32(E100_REG_TIME64_SECS, time_spec.get_full_secs());
         }
         return;
 
@@ -186,7 +186,7 @@ void usrp_e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){
             break;
         default: fe_swap_iq = false;
         }
-        _iface->poke32(UE_REG_RX_FE_SWAP_IQ, fe_swap_iq? 1 : 0);
+        _iface->poke32(E100_REG_RX_FE_SWAP_IQ, fe_swap_iq? 1 : 0);
 
         //set the dsp mux for each channel
         for (size_t i = 0; i < _rx_subdev_spec.size(); i++){
@@ -209,9 +209,9 @@ void usrp_e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){
                 real_mode = true;
                 break;
             }
-            _iface->poke32(UE_REG_DSP_RX_MUX(i),
-                (iq_swap?   UE_FLAG_DSP_RX_MUX_SWAP_IQ   : 0) |
-                (real_mode? UE_FLAG_DSP_RX_MUX_REAL_MODE : 0)
+            _iface->poke32(E100_REG_DSP_RX_MUX(i),
+                (iq_swap?   E100_FLAG_DSP_RX_MUX_SWAP_IQ   : 0) |
+                (real_mode? E100_FLAG_DSP_RX_MUX_REAL_MODE : 0)
             );
         }
         this->update_xport_channel_mapping();
@@ -223,7 +223,7 @@ void usrp_e100_impl::mboard_set(const wax::obj &key, const wax::obj &val){
         //sanity check
         UHD_ASSERT_THROW(_tx_subdev_spec.size() <= E100_NUM_TX_DSPS);
         //set the mux
-        _iface->poke32(UE_REG_TX_FE_MUX, dsp_type1::calc_tx_mux_word(
+        _iface->poke32(E100_REG_TX_FE_MUX, dsp_type1::calc_tx_mux_word(
             _dboard_manager->get_tx_subdev(_tx_subdev_spec.front().sd_name)[SUBDEV_PROP_CONNECTION].as<subdev_conn_t>()
         ));
         return;
diff --git a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp b/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp
deleted file mode 100644
index eace5d7df..000000000
--- a/host/lib/usrp/usrp_e100/usrp_e100_regs.hpp
+++ /dev/null
@@ -1,242 +0,0 @@
-
-
-////////////////////////////////////////////////////////////////
-//
-//         Memory map for embedded wishbone bus
-//
-////////////////////////////////////////////////////////////////
-
-// All addresses are byte addresses.  All accesses are word (16-bit) accesses.
-//  This means that address bit 0 is usually 0.
-//  There are 11 bits of address for the control.
-
-#ifndef INCLUDED_USRP_E100_REGS_HPP
-#define INCLUDED_USRP_E100_REGS_HPP
-
-/////////////////////////////////////////////////////
-// Slave pointers
-
-#define UE_REG_SLAVE(n) ((n)<<7)
-
-/////////////////////////////////////////////////////
-// Slave 0 -- Misc Regs
-
-#define UE_REG_MISC_BASE UE_REG_SLAVE(0)
-
-#define UE_REG_MISC_LED        UE_REG_MISC_BASE + 0
-#define UE_REG_MISC_SW         UE_REG_MISC_BASE + 2
-#define UE_REG_MISC_CGEN_CTRL  UE_REG_MISC_BASE + 4
-#define UE_REG_MISC_CGEN_ST    UE_REG_MISC_BASE + 6
-#define UE_REG_MISC_TEST       UE_REG_MISC_BASE + 8
-#define UE_REG_MISC_RX_LEN     UE_REG_MISC_BASE + 10
-#define UE_REG_MISC_TX_LEN     UE_REG_MISC_BASE + 12
-#define UE_REG_MISC_XFER_RATE  UE_REG_MISC_BASE + 14
-#define UE_REG_MISC_COMPAT     UE_REG_MISC_BASE + 16
-
-/////////////////////////////////////////////////////
-// Slave 1 -- UART
-//   CLKDIV is 16 bits, others are only 8
-
-#define UE_REG_UART_BASE UE_REG_SLAVE(1)
-
-#define UE_REG_UART_CLKDIV  UE_REG_UART_BASE + 0
-#define UE_REG_UART_TXLEVEL UE_REG_UART_BASE + 2
-#define UE_REG_UART_RXLEVEL UE_REG_UART_BASE + 4
-#define UE_REG_UART_TXCHAR  UE_REG_UART_BASE + 6
-#define UE_REG_UART_RXCHAR  UE_REG_UART_BASE + 8
-
-/////////////////////////////////////////////////////
-// Slave 2 -- SPI Core
-//   This should be accessed through the IOCTL
-//   Users should not touch directly
-
-#define UE_REG_SPI_BASE UE_REG_SLAVE(2)
-
-//spi slave constants
-#define UE_SPI_SS_AD9522    (1 << 3)
-#define UE_SPI_SS_AD9862    (1 << 2)
-#define UE_SPI_SS_TX_DB     (1 << 1)
-#define UE_SPI_SS_RX_DB     (1 << 0)
-
-////////////////////////////////////////////////
-// Slave 3 -- I2C Core
-//   This should be accessed through the IOCTL
-//   Users should not touch directly
-
-#define UE_REG_I2C_BASE UE_REG_SLAVE(3)
-
-
-////////////////////////////////////////////////
-// Slave 4 -- GPIO
-
-#define UE_REG_GPIO_BASE UE_REG_SLAVE(4)
-
-#define UE_REG_GPIO_RX_IO      UE_REG_GPIO_BASE + 0
-#define UE_REG_GPIO_TX_IO      UE_REG_GPIO_BASE + 2
-#define UE_REG_GPIO_RX_DDR     UE_REG_GPIO_BASE + 4
-#define UE_REG_GPIO_TX_DDR     UE_REG_GPIO_BASE + 6
-#define UE_REG_GPIO_RX_SEL     UE_REG_GPIO_BASE + 8
-#define UE_REG_GPIO_TX_SEL     UE_REG_GPIO_BASE + 10
-#define UE_REG_GPIO_RX_DBG     UE_REG_GPIO_BASE + 12
-#define UE_REG_GPIO_TX_DBG     UE_REG_GPIO_BASE + 14
-
-//possible bit values for sel when dbg is 0:
-#define GPIO_SEL_SW    0 // if pin is an output, set by software in the io reg
-#define GPIO_SEL_ATR   1 // if pin is an output, set by ATR logic
-
-//possible bit values for sel when dbg is 1:
-#define GPIO_SEL_DEBUG_0   0 // if pin is an output, debug lines from FPGA fabric
-#define GPIO_SEL_DEBUG_1   1 // if pin is an output, debug lines from FPGA fabric
-
-///////////////////////////////////////////////////
-// Slave 6 -- ATR Controller
-//   16 regs
-
-#define UE_REG_ATR_BASE  UE_REG_SLAVE(6)
-
-#define	UE_REG_ATR_IDLE_RXSIDE  UE_REG_ATR_BASE + 0
-#define	UE_REG_ATR_IDLE_TXSIDE  UE_REG_ATR_BASE + 2
-#define UE_REG_ATR_INTX_RXSIDE  UE_REG_ATR_BASE + 4
-#define UE_REG_ATR_INTX_TXSIDE  UE_REG_ATR_BASE + 6
-#define	UE_REG_ATR_INRX_RXSIDE  UE_REG_ATR_BASE + 8
-#define	UE_REG_ATR_INRX_TXSIDE  UE_REG_ATR_BASE + 10
-#define	UE_REG_ATR_FULL_RXSIDE  UE_REG_ATR_BASE + 12
-#define	UE_REG_ATR_FULL_TXSIDE  UE_REG_ATR_BASE + 14
-
-///////////////////////////////////////////////////
-// Slave 7 -- Readback Mux 32
-
-#define UE_REG_RB_MUX_32_BASE  UE_REG_SLAVE(7)
-
-#define UE_REG_RB_TIME_NOW_SECS   UE_REG_RB_MUX_32_BASE + 0
-#define UE_REG_RB_TIME_NOW_TICKS  UE_REG_RB_MUX_32_BASE + 4
-#define UE_REG_RB_TIME_PPS_SECS   UE_REG_RB_MUX_32_BASE + 8
-#define UE_REG_RB_TIME_PPS_TICKS  UE_REG_RB_MUX_32_BASE + 12
-#define UE_REG_RB_MISC_TEST32     UE_REG_RB_MUX_32_BASE + 16
-
-////////////////////////////////////////////////////
-// Slave 8 -- Settings Bus
-//
-// Output-only, no readback, 64 registers total
-//  Each register must be written 64 bits at a time
-//  First the address xxx_xx00 and then xxx_xx10
-
-// 64 total regs in address space
-#define UE_SR_RX_CTRL0 0       // 9 regs (+0 to +8)
-#define UE_SR_RX_DSP0 10       // 4 regs (+0 to +3)
-#define UE_SR_RX_CTRL1 16      // 9 regs (+0 to +8)
-#define UE_SR_RX_DSP1 26       // 4 regs (+0 to +3)
-#define UE_SR_TX_CTRL 32       // 4 regs (+0 to +3)
-#define UE_SR_TX_DSP 38        // 3 regs (+0 to +2)
-
-#define UE_SR_TIME64 42        // 6 regs (+0 to +5)
-#define UE_SR_RX_FRONT 48      // 5 regs (+0 to +4)
-#define UE_SR_TX_FRONT 54      // 5 regs (+0 to +4)
-
-#define UE_SR_REG_TEST32 60    // 1 reg
-#define UE_SR_CLEAR_RX_FIFO 61 // 1 reg
-#define UE_SR_CLEAR_TX_FIFO 62 // 1 reg
-#define UE_SR_GLOBAL_RESET 63  // 1 reg
-
-#define UE_REG_SR_ADDR(n) (UE_REG_SLAVE(8) + (4*(n)))
-
-#define UE_REG_SR_MISC_TEST32        UE_REG_SR_ADDR(UE_SR_REG_TEST32)
-
-/////////////////////////////////////////////////
-// Magic reset regs
-////////////////////////////////////////////////
-#define UE_REG_CLEAR_RX           UE_REG_SR_ADDR(UE_SR_CLEAR_RX_FIFO)
-#define UE_REG_CLEAR_TX           UE_REG_SR_ADDR(UE_SR_CLEAR_RX_FIFO)
-#define UE_REG_GLOBAL_RESET       UE_REG_SR_ADDR(UE_SR_GLOBAL_RESET)
-
-/////////////////////////////////////////////////
-// DSP RX Regs
-////////////////////////////////////////////////
-#define UE_REG_DSP_RX_HELPER(which, offset) ((which == 0)? \
-    (UE_REG_SR_ADDR(UE_SR_RX_DSP0 + offset)) : \
-    (UE_REG_SR_ADDR(UE_SR_RX_DSP1 + offset)))
-
-#define UE_REG_DSP_RX_FREQ(which)       UE_REG_DSP_RX_HELPER(which, 0)
-#define UE_REG_DSP_RX_DECIM(which)      UE_REG_DSP_RX_HELPER(which, 2)
-#define UE_REG_DSP_RX_MUX(which)        UE_REG_DSP_RX_HELPER(which, 3)
-
-#define UE_FLAG_DSP_RX_MUX_SWAP_IQ   (1 << 0)
-#define UE_FLAG_DSP_RX_MUX_REAL_MODE (1 << 1)
-
-///////////////////////////////////////////////////
-// RX CTRL regs
-///////////////////////////////////////////////////
-#define UE_REG_RX_CTRL_HELPER(which, offset) ((which == 0)? \
-    (UE_REG_SR_ADDR(UE_SR_RX_CTRL0 + offset)) : \
-    (UE_REG_SR_ADDR(UE_SR_RX_CTRL1 + offset)))
-
-#define UE_REG_RX_CTRL_STREAM_CMD(which)     UE_REG_RX_CTRL_HELPER(which, 0)
-#define UE_REG_RX_CTRL_TIME_SECS(which)      UE_REG_RX_CTRL_HELPER(which, 1)
-#define UE_REG_RX_CTRL_TIME_TICKS(which)     UE_REG_RX_CTRL_HELPER(which, 2)
-#define UE_REG_RX_CTRL_CLEAR(which)          UE_REG_RX_CTRL_HELPER(which, 3)
-#define UE_REG_RX_CTRL_VRT_HDR(which)        UE_REG_RX_CTRL_HELPER(which, 4)
-#define UE_REG_RX_CTRL_VRT_SID(which)        UE_REG_RX_CTRL_HELPER(which, 5)
-#define UE_REG_RX_CTRL_VRT_TLR(which)        UE_REG_RX_CTRL_HELPER(which, 6)
-#define UE_REG_RX_CTRL_NSAMPS_PP(which)      UE_REG_RX_CTRL_HELPER(which, 7)
-#define UE_REG_RX_CTRL_NCHANNELS(which)      UE_REG_RX_CTRL_HELPER(which, 8)
-
-/////////////////////////////////////////////////
-// RX FE
-////////////////////////////////////////////////
-#define UE_REG_RX_FE_SWAP_IQ             UE_REG_SR_ADDR(UE_SR_RX_FRONT + 0) //lower bit
-#define UE_REG_RX_FE_MAG_CORRECTION      UE_REG_SR_ADDR(UE_SR_RX_FRONT + 1) //18 bits
-#define UE_REG_RX_FE_PHASE_CORRECTION    UE_REG_SR_ADDR(UE_SR_RX_FRONT + 2) //18 bits
-#define UE_REG_RX_FE_OFFSET_I            UE_REG_SR_ADDR(UE_SR_RX_FRONT + 3) //18 bits
-#define UE_REG_RX_FE_OFFSET_Q            UE_REG_SR_ADDR(UE_SR_RX_FRONT + 4) //18 bits
-
-/////////////////////////////////////////////////
-// DSP TX Regs
-////////////////////////////////////////////////
-#define UE_REG_DSP_TX_FREQ          UE_REG_SR_ADDR(UE_SR_TX_DSP + 0)
-#define UE_REG_DSP_TX_SCALE_IQ      UE_REG_SR_ADDR(UE_SR_TX_DSP + 1)
-#define UE_REG_DSP_TX_INTERP_RATE   UE_REG_SR_ADDR(UE_SR_TX_DSP + 2)
-
-///////////////////////////////////////////////////
-// TX CTRL regs
-///////////////////////////////////////////////////
-#define UE_REG_TX_CTRL_NUM_CHAN       UE_REG_SR_ADDR(UE_SR_TX_CTRL + 0)
-#define UE_REG_TX_CTRL_CLEAR_STATE    UE_REG_SR_ADDR(UE_SR_TX_CTRL + 1)
-#define UE_REG_TX_CTRL_REPORT_SID     UE_REG_SR_ADDR(UE_SR_TX_CTRL + 2)
-#define UE_REG_TX_CTRL_POLICY         UE_REG_SR_ADDR(UE_SR_TX_CTRL + 3)
-#define UE_REG_TX_CTRL_CYCLES_PER_UP  UE_REG_SR_ADDR(UE_SR_TX_CTRL + 4)
-#define UE_REG_TX_CTRL_PACKETS_PER_UP UE_REG_SR_ADDR(UE_SR_TX_CTRL + 5)
-
-#define UE_FLAG_TX_CTRL_POLICY_WAIT          (0x1 << 0)
-#define UE_FLAG_TX_CTRL_POLICY_NEXT_PACKET   (0x1 << 1)
-#define UE_FLAG_TX_CTRL_POLICY_NEXT_BURST    (0x1 << 2)
-
-/////////////////////////////////////////////////
-// TX FE
-////////////////////////////////////////////////
-#define UE_REG_TX_FE_DC_OFFSET_I         UE_REG_SR_ADDR(UE_SR_TX_FRONT + 0) //24 bits
-#define UE_REG_TX_FE_DC_OFFSET_Q         UE_REG_SR_ADDR(UE_SR_TX_FRONT + 1) //24 bits
-#define UE_REG_TX_FE_MAC_CORRECTION      UE_REG_SR_ADDR(UE_SR_TX_FRONT + 2) //18 bits
-#define UE_REG_TX_FE_PHASE_CORRECTION    UE_REG_SR_ADDR(UE_SR_TX_FRONT + 3) //18 bits
-#define UE_REG_TX_FE_MUX                 UE_REG_SR_ADDR(UE_SR_TX_FRONT + 4) //8 bits (std output = 0x10, reversed = 0x01)
-
-/////////////////////////////////////////////////
-// VITA49 64 bit time (write only)
-////////////////////////////////////////////////
-#define UE_REG_TIME64_SECS      UE_REG_SR_ADDR(UE_SR_TIME64 + 0)
-#define UE_REG_TIME64_TICKS     UE_REG_SR_ADDR(UE_SR_TIME64 + 1)
-#define UE_REG_TIME64_FLAGS     UE_REG_SR_ADDR(UE_SR_TIME64 + 2)
-#define UE_REG_TIME64_IMM       UE_REG_SR_ADDR(UE_SR_TIME64 + 3)
-#define UE_REG_TIME64_TPS       UE_REG_SR_ADDR(UE_SR_TIME64 + 4)
-#define UE_REG_TIME64_MIMO_SYNC UE_REG_SR_ADDR(UE_SR_TIME64 + 5)
-
-//pps flags (see above)
-#define UE_FLAG_TIME64_PPS_NEGEDGE (0 << 0)
-#define UE_FLAG_TIME64_PPS_POSEDGE (1 << 0)
-#define UE_FLAG_TIME64_PPS_SMA     (0 << 1)
-#define UE_FLAG_TIME64_PPS_MIMO    (1 << 1)
-
-#define UE_FLAG_TIME64_LATCH_NOW 1
-#define UE_FLAG_TIME64_LATCH_NEXT_PPS 0
-
-#endif
-