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authorNick Foster <nick@nerdnetworks.org>2010-08-17 18:35:11 -0700
committerNick Foster <nick@nerdnetworks.org>2010-08-17 18:35:11 -0700
commit9d10efa5f0f81e1a971e92b28ba7f38e0384fdab (patch)
tree7b797016a4da8625dabc41c9bcc9ee0216092507 /host/lib
parent40faee2e6d87f7364a0c0c2cf310f1483c0331cf (diff)
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UDP firmware update support for USRP2P.
The hooks are in there for USRP2, but without CPLD changes it won't support it. Added an app host/utils/usrp2p_fw_update.py to write to USRP2P over the wire. Lots of TODOs in that file. Caveat -- fw_common.h, bootloader_utils.h, and the .py app MUST ALL AGREE!
Diffstat (limited to 'host/lib')
-rw-r--r--host/lib/usrp/usrp2/fw_common.h50
1 files changed, 49 insertions, 1 deletions
diff --git a/host/lib/usrp/usrp2/fw_common.h b/host/lib/usrp/usrp2/fw_common.h
index fc1e6f2a7..320ed7d77 100644
--- a/host/lib/usrp/usrp2/fw_common.h
+++ b/host/lib/usrp/usrp2/fw_common.h
@@ -34,7 +34,7 @@ extern "C" {
//fpga and firmware compatibility numbers
#define USRP2_FPGA_COMPAT_NUM 1
-#define USRP2_FW_COMPAT_NUM 5
+#define USRP2_FW_COMPAT_NUM 6
//used to differentiate control packets over data port
#define USRP2_INVALID_VRT_HEADER 0
@@ -43,6 +43,7 @@ extern "C" {
// Dynamic and/or private ports: 49152-65535
#define USRP2_UDP_CTRL_PORT 49152
#define USRP2_UDP_DATA_PORT 49153
+#define USRP2_UDP_UPDATE_PORT 49154 //for firmware upgrade commands
////////////////////////////////////////////////////////////////////////
// I2C addresses
@@ -93,6 +94,35 @@ typedef enum{
} usrp2_ctrl_id_t;
+typedef enum {
+ USRP2_FW_UPDATE_ID_WAT = ' ',
+
+ USRP2_FW_UPDATE_ID_OHAI_LOL = 'a',
+ USRP2_FW_UPDATE_ID_OHAI_OMG = 'A',
+
+ USRP2_FW_UPDATE_ID_WATS_TEH_FLASH_INFO_LOL = 'f',
+ USRP2_FW_UPDATE_ID_HERES_TEH_FLASH_INFO_OMG = 'F',
+
+ USRP2_FW_UPDATE_ID_ERASE_TEH_FLASHES_LOL = 'e',
+ USRP2_FW_UPDATE_ID_ERASING_TEH_FLASHES_OMG = 'E',
+
+ USRP2_FW_UPDATE_ID_R_U_DONE_ERASING_LOL = 'd',
+ USRP2_FW_UPDATE_ID_IM_DONE_ERASING_OMG = 'D',
+ USRP2_FW_UPDATE_ID_NOPE_NOT_DONE_ERASING_OMG = 'B',
+
+ USRP2_FW_UPDATE_ID_WRITE_TEH_FLASHES_LOL = 'w',
+ USRP2_FW_UPDATE_ID_WROTE_TEH_FLASHES_OMG = 'W',
+
+ USRP2_FW_UPDATE_ID_READ_TEH_FLASHES_LOL = 'r',
+ USRP2_FW_UPDATE_ID_KK_READ_TEH_FLASHES_OMG = 'R',
+
+ USRP2_FW_UPDATE_ID_RESET_MAH_COMPUTORZ_LOL = 's',
+ USRP2_FW_UPDATE_ID_RESETTIN_TEH_COMPUTORZ_OMG = 'S',
+
+ USRP2_FW_UPDATE_ID_KTHXBAI = '~'
+
+} usrp2_fw_update_id_t;
+
typedef enum{
USRP2_DIR_RX = 'r',
USRP2_DIR_TX = 't'
@@ -137,6 +167,24 @@ typedef struct{
} data;
} usrp2_ctrl_data_t;
+typedef struct {
+ __stdint(uint32_t) proto_ver;
+ __stdint(uint32_t) id;
+ __stdint(uint32_t) seq;
+ union {
+ __stdint(uint32_t) ip_addr;
+ struct {
+ __stdint(uint32_t) flash_addr;
+ __stdint(uint32_t) length;
+ __stdint(uint8_t) data[256];
+ } flash_args;
+ struct {
+ __stdint(uint32_t) sector_size_bytes;
+ __stdint(uint32_t) memory_size_bytes;
+ } flash_info_args;
+ } data;
+} udp_fw_update_data_t;
+
#undef __stdint
#ifdef __cplusplus
}